ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 127
ATTINY44-15MZ
Manufacturer Part Number
ATTINY44-15MZ
Description
MCU AVR 4K FLASH 15MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY44-15MZ.pdf
(225 pages)
Specifications of ATTINY44-15MZ
Package / Case
20-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
12
Eeprom Size
256 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
256 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY44-15MZ
Manufacturer:
ATMEL
Quantity:
1 000
Part Number:
ATTINY44-15MZ
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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16.3.4
7701E–AVR–02/11
Two-wire Mode
The USI two-wire mode is compliant with the Inter-IC (I2C or TWI) bus protocol, but without
slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL
and SDA.
Figure 16-4. Two-wire Mode Operation, Simplified Diagram
Figure 16-4 on page 127
one as slave. Only the physical layer is shown because the system operation is highly depen-
dent of the communication scheme used. The main differences between the master and slave
operation at this level are that the serial clock generation is always done by the master, and
only the slave uses the clock control unit. Clock generation must be implemented in software,
but the shift operation is done automatically by both devices. Note that only clocking on the
negative edge to shift data is practical in this mode. The slave can insert wait states at the start
or end of a transfer by forcing the SCL clock low. This means that the master must always
check if the SCL line was actually released after it has generated a positive edge.
Because the clock also increments the counter, a counter overflow can be used to indicate
that the transfer has completed. The master generates clock by the by toggling the USCK pin
via the PORT register.
The data direction is not given by the physical layer. A protocol, like the one used by the
TWI-bus, must be implemented to control the data flow.
SLAVE
MASTER
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
shows two USI units operating in two-wire mode, one as master and
Atmel ATtiny24/44/84 [Preliminary]
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
Two-wire Clock
Control Unit
PORTxn
HOLD
SCL
SDA
SCL
SDA
SCL
VCC
127
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