ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 23

• Manufacturer Part Number: ATTINY44-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7701E–AVR–02/11
• Bit 7 – Res: Reserved Bit
This bit is reserved for future use, and will always read as 0 in Atmel
compatibility with future AVR
mask out this bit.
• Bit 6 – Res: Reserved Bit
This bit is reserved in the Atmel ATtiny24/44/84 and will always read as zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Mode Bits
The EEPROM programming mode bits define which programming action will be triggered
when writing EEPE. It is possible to program data in one atomic operation (erase the old value
and program the new value) or split the erase and write operations into two separate opera-
tions. The programming times for the different modes are shown in Table 6-1. While EEPE is
set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00
unless the EEPROM is busy programming.
Table 6-1.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to logical one enables the EEPROM ready interrupt if the I-bit in SREG is set.
Writing EERIE to logical zero disables the interrupt. The EEPROM ready interrupt generates a
constant interrupt when non-volatile memory is ready for programming.
• Bit 2 – EEMPE: EEPROM Master Program Enable
The EEMPE bit determines whether writing EEPE to logical one will have effect or not. When
EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected
address. If EEMPE is logical zero, setting EEPE will have no effect. When EEMPE has been
written to logical one by software, hardware clears the bit to logical zero after four clock cycles.
• Bit 1 – EEPE: EEPROM Program Enable
The EEPROM program enable bit, EEPE, is the programming enable signal to the EEPROM.
When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting.
The EEMPE bit must be written to logical one before a logical one is written to EEPE, other-
wise no EEPROM write will take place. When the write access time has elapsed, the EEPE bit
is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the
next instruction is executed.
EEPM1
0
0
1
1
EEPM0
EEPROM Mode Bits
0
1
0
1
Programming
Atmel ATtiny24/44/84 [Preliminary]
3.4ms
1.8ms
1.8ms
Time
–
®
devices, always write this bit to a logical zero. After reading,
Operation
Erase and Write in one operation (Atomic Operation)
Erase Only
Write Only
Reserved for future use
®
ATtiny24/44/84. For
23