ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 16

• Manufacturer Part Number: ATTINY44-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.1
16
Atmel ATtiny24/44/84 [Preliminary]
Data Memory Access Times
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and 128/256/512 bytes of internal
data SRAM in the Atmel
modes. The Register File is described in
Figure 6-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
page
Figure 6-3.
16.
Address
Data Memory Map
On-chip Data SRAM Access Cycles
clk
Data
Data
WR
CPU
RD
®
(128/256/512 x 8)
64 I/O Registers
Data Memory
ATtiny24/44/84 are all accessible through all these addressing
Internal SRAM
Compute Address
32 Registers
T1
Memory Access Instruction
“General Purpose Register File” on page
0x0DF/0x015F/0x025F
0x0000 - 0x001F
0x0020 - 0x005F
0x0060
Address valid
T2
CPU
cycles as described in
Next Instruction
T3
Figure 6-3 on
7701E–AVR–02/11
10.