ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 132

• Manufacturer Part Number: ATTINY44-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

132
Atmel ATtiny24/44/84 [Preliminary]
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the start condition detector interrupt. If there is a pending inter-
rupt when the USISIE and the global interrupt enable flag are set to one, this will immediately
be executed. See the USISIF bit description in
further details.
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt
when the USIOIE and the Global Interrupt Enable Flag are set to one, this will immediately be
executed. See the USIOIF bit description in
further details.
• Bit 5..4 – USIWM1..0: Wire Mode
These bits set the type of wire mode to be used. Basically, only the function of the outputs are
affected by these bits. Data and clock inputs are not affected by the mode selected, and will
always have the same function. The counter and shift register can, therefore, be clocked
externally, and data input sampled, even when outputs are disabled. The relation between
USIWM1..0 and USI operation is summarized in
Table 16-1.
Note:
USIWM1
0
0
1
1
1. The DI and USCK pins are renamed to serial data (SDA) and serial clock (SCL), respec-
tively, to avoid confusion between the modes of operation.
USIWM0
Relations between USIWM1..0 and the USI Operation
0
1
0
1
Description
Outputs, clock hold, and start detector disabled. Port pins operate as normal.
Three-wire mode. Uses DO, DI, and USCK pins.
The Data Output (DO) pin overrides the corresponding bit in the PORT
Register in this mode. However, the corresponding DDR bit still controls the
data direction. When the port pin is set as input the pins pull-up is controlled
by the PORT bit.
The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal
port operation. When operating as master, clock pulses are software
generated by toggling the PORT Register, while the data direction is set to
output. The USITC bit in the USICR Register can be used for this purpose.
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins
The serial data (SDA) and the serial clock (SCL) pins are bi-directional and
use open-collector output drivers. The output drivers are enabled by setting
the corresponding bit for SDA and SCL in the DDR register.
When the output driver is enabled for the SDA pin, the output driver will force
the SDA line low if the output of the shift register or the corresponding bit in
the PORT register is zero. Otherwise, the SDA line will not be driven (i.e., it is
released). When the SCL pin output driver is enabled, the SCL line will be
forced low if the corresponding bit in the PORT register is zero, or by the start
detector. Otherwise the SCL line will not be driven.
The SCL line is held low when a start detector detects a start condition and
the output is enabled. Clearing the start condition flag (USISIF) releases the
line. The SDA and SCL pin inputs are not affected by enabling this mode.
Pull-ups on the SDA and SCL port pins are disabled in two-wire mode.
Two-wire mode. Uses SDA and SCL pins.
Same operation as for the Two-wire mode described above, except that the
SCL line is also held low when a counter overflow occurs, and is held low until
the Counter Overflow Flag (USIOIF) is cleared.
“USISR – USI Status Register” on page 130
“USISR – USI Status Register” on page 130
Table
16-1.
(1)
.
7701E–AVR–02/11
for
for