ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 162

• Manufacturer Part Number: ATTINY44-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page
Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during
the entire Page Write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to logical one at the same time as SPMEN, the next SPM instruction within
four clock cycles executes a page erase. The page address is taken from the high part of the
Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion
of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is
halted during the entire page erase operation.
• Bit 0 – SPMEN: Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If written to logical one
together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have
a special meaning (see description above). If only SPMEN is written, the following SPM
instruction will store the value in R1:R0 in the temporary page buffer addressed by the
Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion
of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During
page erase and page write, the SPMEN bit remains high until the operation is completed.
Writing any combination other than "10001", "01001", "00101", "00011", or "00001" in the
lower five bits will have no effect.
Atmel ATtiny24/44/84 [Preliminary]
162
7701E–AVR–02/11