ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 55
![MCU AVR 4K FLASH 15MHZ 20-QFN](/photos/12/32/123214/20-qfn-pc_sml.jpg)
ATTINY44-15MZ
Manufacturer Part Number
ATTINY44-15MZ
Description
MCU AVR 4K FLASH 15MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY44-15MZ.pdf
(225 pages)
Specifications of ATTINY44-15MZ
Package / Case
20-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
12
Eeprom Size
256 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
256 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY44-15MZ
Manufacturer:
ATMEL
Quantity:
1 000
Part Number:
ATTINY44-15MZ
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 55 of 225
- Download datasheet (4Mb)
11.2.5
7701E–AVR–02/11
PCMSK0 – Pin Change Mask Register 0
• Bits 3..0 – PCINT11..8: Pin Change Enable Mask 11..8
Each PCINT11..8 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT11..8 is set (logical one) and the PCIE1 bit in GIMSK is set, pin change interrupt
is enabled on the corresponding I/O pin. If PCINT11..8 is cleared, pin change interrupt on the
corresponding I/O pin is disabled.
• Bits 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT7..0 is set (logical one) and the PCIE0 bit in GIMSK is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the cor-
responding I/O pin is disabled.
Bit
0x12 (0x32)
Read/Write
Initial Value
PCINT7
R/W
7
0
PCINT6
R/W
6
0
Atmel ATtiny24/44/84 [Preliminary]
PCINT5
R/W
5
0
PCINT4
R/W
4
0
PCINT3
R/W
3
0
PCINT2
R/W
2
0
PCINT1
R/W
1
0
PCINT0
R/W
0
0
PCMSK0
55
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