ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 150

• Manufacturer Part Number: ATTINY44-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

150
Atmel ATtiny24/44/84 [Preliminary]
Table 18-4.
Notes:
See
selection of offset calibration channels. The MUX0 bit works as a gain selection bit for differen-
tial channels, as shown in
gain is selected, and when it is set (one) 20x gain is selected. For normal differential channel
pairs, the MUX5 bit works as a polarity reversal bit. Toggling of the MUX5 bit reverses the pos-
itive and negative channel orientation.
For offset calibration purposes, the offset of certain differential channels can be measured by
selecting the same input for both negative and positive input. This calibration can be done for
ADC0, ADC3, and ADC7.
detailed manner.
Table 18-5 on page 151
1. See
2.
3. For offset calibration only.See
Reserved for reversal differential channels
“Temperature Measurement” on page 148
Reserved for differential channels
Single Ended Input Channel Selections.
Reserved for offset calibration
Table 18-5 on page 151
Single Ended Input
ADC0 (PA0)
ADC1 (PA1)
ADC2 (PA2)
ADC3 (PA3)
ADC4 (PA4)
ADC5 (PA5)
ADC6 (PA6)
ADC7 (PA7)
0V (AGND)
1.1V (I Ref)
ADC8
“ADC Operation” on page 138
Table 18-5 on page
for details of selection of differential input channels as well as
(2)
for details.
Table 18-5 on page 151
(3)
(1)
(1)
151. When the MUX0 bit is cleared (zero) 1x
describes offset calibration in a more
and
“ADC Operation” on page 138
001000 - 011111
100011 - 100111
101000 - 111111
MUX5..0
000000
000001
000010
000011
000100
000101
000110
000111
100000
100001
100010
7701E–AVR–02/11