ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 97

• Manufacturer Part Number: ATTINY44-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5
7701E–AVR–02/11
Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter
unit.
Figure 14-2. Counter Unit Block Diagram
Signal description (internal signals):
The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high (TCNT1H)
containing the upper eight bits of the counter, and counter low (TCNT1L) containing the lower
eight bits. The TCNT1H register can only be indirectly accessed by the CPU. When the CPU
does an access to the TCNT1H I/O location, the CPU accesses the high byte temporary regis-
ter (TEMP). The temporary register is updated with the TCNT1H value when TCNT1L is
read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This
allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the
8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1
register when the counter is counting that will give unpredictable results. The special cases
are described in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decre-
mented at each timer clock (clkT1). The clkT1 can be generated from an external or internal
clock source, selected by the clock select bits (CS12:0). When no clock source is selected
(CS12:0 = 0,) the timer is stopped. However, the TCNT1 value can be accessed by the CPU
independently of whether clkT1 is present or not. A CPU write overrides (has priority over)
all counter clear or count operations.
The counting sequence is determined by the setting of the waveform generation mode bits
(WGM13:0) located in timer/counter control registers A and B (TCCR1A and TCCR1B). There
are close connections between how the counter behaves (counts) and how waveforms are
generated on the output compare outputs (OC1x). For more details about advanced counting
sequences and waveform generation, see
Figure 14-2 on page 97
Count
Direction
Clear
clk
TOP
BOTTOM
T
TCNTnH (8-bit)
1
TEMP (8-bit)
TCNTn (16-bit Counter)
DATA BUS
TCNTnL (8-bit)
(8-bit)
Atmel ATtiny24/44/84 [Preliminary]
shows a block diagram of the counter and its surroundings.
Increment or decrement TCNT1 by 1.
Select between increment and decrement.
Clear TCNT1 (set all bits to zero).
Timer/Counter clock.
Signal that TCNT1 has reached maximum value.
Signal that TCNT1 has reached minimum value (zero).
Direction
Count
Clear
“Modes of Operation” on page
Control Logic
TOP
BOTTOM
TOVn
(Int.Req.)
clk
Tn
Clock Select
( From Prescaler )
Detector
Edge
103.
Tn
97