ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 35

• Manufacturer Part Number: ATTINY44-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3
8.4
8.5
8.6
7701E–AVR–02/11
ADC Noise Reduction Mode
Power-down Mode
Standby Mode
Software BOD Disable
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,
the Analog Comparator can be powered down by setting the ACD bit in the Analog Compara-
tor Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If
the ADC is enabled, a conversion starts automatically when this mode is entered.
When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and
the Watchdog to continue operating (if enabled). This sleep mode halts clk
clk
This improves the noise environment for the ADC, enabling higher resolution measurements.
If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from
the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a
Brown-out Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a
pin change interrupt can wake up the MCU from ADC Noise Reduction mode.
When the SM1..0 bits are written to “10”, the SLEEP instruction makes the MCU enter
power-down mode. In this mode, the oscillator is stopped, while the external interrupts and the
watchdog continue operating (if enabled). Only an external reset, a watchdog reset, a
brown-out reset, an external level interrupt on INT0, or a pin change interrupt can wake up the
MCU. This sleep mode halts all generated clocks, allowing operation of asynchronous mod-
ules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. See
page 52
When the SM1..0 bits are 11 and an external crystal/resonator clock option is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to
Power-down with the exception that the Oscillator is kept running. From Standby mode, the
device wakes up in six clock cycles.
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses (see
page
devices it is possible to save power by disabling the BOD by software in Power-Down and
Stand-By sleep modes. The sleep mode power consumption will then be at the same level as
when BOD is globally disabled by fuses.
If BOD is disabled by software, the BOD function is turned off immediately after entering the
sleep mode. Upon wake-up from sleep, BOD is automatically enabled again. This ensures
safe operation in case the V
FLASH
164), the BOD is actively monitoring the supply voltage during a sleep period. In some
, while allowing the other clocks to run.
for details
Atmel ATtiny24/44/84 [Preliminary]
CC
level has dropped during the sleep period.
“External Interrupts” on
I/O
, clk
Table 21-4 on
CPU
, and
35