ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 143
![IC MCU 32BIT 256KB FLASH 48QFN](/photos/7/34/73471/48-vqfn-6_543-5130_01-4_sml.jpg)
ATSAM3S4AA-MU
Manufacturer Part Number
ATSAM3S4AA-MU
Description
IC MCU 32BIT 256KB FLASH 48QFN
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4AA-MU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S4AA-MU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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10.18.6
10.18.6.1
10.18.6.2
10.18.6.3
10.18.6.4
10.18.6.5
6500C–ATARM–8-Feb-11
MRS
MRS
Syntax
Operation
Restrictions
Condition flags
Examples
R0, PRIMASK ; Read PRIMASK value and write it to R0
Move the contents of a special register to a general-purpose register.
where:
cond
Rd
spec_reg
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR,
for example to clear the Q flag.
In process swap code, the programmers model state of the process being swapped out must be
saved, including relevant PSR contents. Similarly, the state of the process being swapped in
must also be restored. These operations use MRS in the state-saving instruction sequence and
MSR in the state-restoring instruction sequence.
BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.
See
Rd must not be SP and must not be PC.
This instruction does not change the flags.
MRS{cond} Rd, spec_reg
“MSR” on page
is an optional condition code, see
is the destination register.
can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
144.
“Conditional execution” on page
SAM3S Preliminary
84.
143
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