ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 849
ATSAM3S4AA-MU
Manufacturer Part Number
ATSAM3S4AA-MU
Description
IC MCU 32BIT 256KB FLASH 48QFN
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4AA-MU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S4AA-MU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 849 of 1118
- Download datasheet (24Mb)
6500C–ATARM–8-Feb-11
The PWM master clock (MCK) is divided in the clock generator module to provide different
clocks available for all channels. Each channel can independently select one of the divided
clocks.
The clock generator is divided in three blocks:
Each linear divider can independently divide one of the clocks of the modulo n counter. The
selection of the clock to be divided is made according to the PREA (PREB) field of the PWM
Clock register (PWM_CLK). The resulting clock clkA (clkB) is the clock selected divided by DIVA
(DIVB) field value.
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) are set to 0. This implies
that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock ”MCK”. This sit-
uation is also true when the PWM master clock is turned off through the Power Management
Controller.
CAUTION:
• Before using the PWM macrocell, the programmer must first enable the PWM clock in the
Power Management Controller (PMC).
– a modulo n counter which provides 11 clocks: F
– two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and
F
clkB
MCK
/16, F
MCK
/32, F
MCK
/64, F
MCK
/128, F
MCK
/256, F
MCK
MCK
SAM3S Preliminary
, F
MCK
/512, F
/2, F
MCK
MCK
/1024
/4, F
MCK
/8,
849
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