ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 435
ATSAM3S4AA-MU
Manufacturer Part Number
ATSAM3S4AA-MU
Description
IC MCU 32BIT 256KB FLASH 48QFN
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4AA-MU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S4AA-MU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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26.12 Clock Failure Detector
6500C–ATARM–8-Feb-11
The clock failure detector allows to monitor the 3 to 20 MHz Crystal or Ceramic Resonator-
based oscillator and to detect an eventual defect of this oscillator (for example if the crystal is
unconnected).
The clock failure detector can be enabled or disabled by means of the CFDEN bit in the PMC
Clock Generator Main Oscillator Register (CKGR_MOR). After reset, the detector is disabled.
However, if the 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator is disabled, the
clock failure detector is disabled too.
A failure is detected by means of a counter incrementing on the 3 to 20 MHzCrystal oscillator or
Ceramic Resonator-based oscillator clock edge and timing logic clocked on the slow clock RC
oscillator controlling the counter. The counter is cleared when the slow clock RC oscillator signal
is low and enabled when the slow clock RC oscillator is high. Thus the failure detection time is 1
slow clock RC oscillator clock period. If, during the high level period of slow clock RC oscillator,
less than 8 fast crystal clock periods have been counted, then a failure is declared.
If a failure of the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is detected,
the CFDEV flag is set in the PMC Status Register (PMC_SR), and can generate an interrupt if it
is not masked. The interrupt remains active until a read operation in the PMC_SR register. The
user can know the status of the clock failure detector at any time by reading the CFDS bit in the
PMC_SR register.
If the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is selected as the source
clock of MAINCK (MOSCSEL = 1), and if the Master Clock Source is PLLACK or PLLBCK (CSS
= 2 or 3), then a clock failure detection switches automatically the Master Clock on MAINCK.
Then whatever the PMC configuration is, a clock failure detection switches automatically
MAINCK on the 4/8/12 MHz Fast RC Oscillator clock. If the Fast RC oscillator is disabled when a
clock failure detection occurs, it is automatically re-enabled by the clock failure detection
mechanism.
It takes 2 slow clock RC oscillator cycles to detect and switch from the 3 to 20 MHz Crystal or
Ceramic Resonator-based oscillator to the 4/8/12 MHz Fast RC Oscillator if the Master Clock
source is Main Clock, or 3 slow clock RC oscillator cycles if the Master Clock source is PLLACK
or PLLBACK.
A clock failure detection activates a fault output that is connected to the Pulse Width Modulator
(PWM) Controller. With this connection, the PWM controller is able to force its outputs and to
protect the driven device, if a clock failure is detected. This fault output remains active until the
defect is detected and until it is not cleared by the bit FOCLR in the PMC Fault Output Clear
Register (PMC_FOCR).
The user can know the status of the fault output at any time by reading the bit
PMC_SR register.
SAM3S Preliminary
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