ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 79
ATSAM3S4AA-MU
Manufacturer Part Number
ATSAM3S4AA-MU
Description
IC MCU 32BIT 256KB FLASH 48QFN
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4AA-MU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S4AA-MU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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10.11 About the instruction descriptions
10.11.1
10.11.2
6500C–ATARM–8-Feb-11
Operands
Restrictions when using PC or SP
The CMSIS also provides a number of functions for accessing the special registers using MRS
and MSR instructions:
Table 10-15. CMSIS intrinsic functions to access the special registers
The following sections give more information about using the instructions:
An instruction operand can be an ARM register, a constant, or another instruction-specific
parameter. Instructions act on the operands and often store the result in a destination register.
When there is a destination register in the instruction, it is usually specified before the operands.
Operands in some instructions are flexible in that they can either be a register or a constant. See
“Flexible second operand”
Many instructions have restrictions on whether you can use the Program Counter (PC) or Stack
Pointer (SP) for the operands or destination register. See instruction descriptions for more
information.
Special register
PRIMASK
FAULTMASK
BASEPRI
CONTROL
MSP
PSP
•
•
•
•
•
•
•
•
“Operands” on page 79
“Restrictions when using PC or SP” on page 79
“Flexible second operand” on page 80
“Shift Operations” on page 81
“Address alignment” on page 83
“PC-relative expressions” on page 84
“Conditional execution” on page 84
“Instruction width selection” on page
Access
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
.
CMSIS function
uint32_t __get_PRIMASK (void)
void __set_PRIMASK (uint32_t value)
uint32_t __get_FAULTMASK (void)
void __set_FAULTMASK (uint32_t value)
uint32_t __get_BASEPRI (void)
void __set_BASEPRI (uint32_t value)
uint32_t __get_CONTROL (void)
void __set_CONTROL (uint32_t value)
uint32_t __get_MSP (void)
void __set_MSP (uint32_t TopOfMainStack)
uint32_t __get_PSP (void)
void __set_PSP (uint32_t TopOfProcStack)
86.
SAM3S Preliminary
79
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