ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 73
ATSAM3S4AA-MU
Manufacturer Part Number
ATSAM3S4AA-MU
Description
IC MCU 32BIT 256KB FLASH 48QFN
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4AA-MU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S4AA-MU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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10.8
10.8.1
10.8.1.1
10.8.1.2
10.8.1.3
10.8.2
10.8.2.1
6500C–ATARM–8-Feb-11
Power management
Entering sleep mode
Wakeup from sleep mode
Wait for interrupt
Wait for event
Sleep-on-exit
Wakeup from WFI or sleep-on-exit
The Cortex-M3 processor sleep modes reduce power consumption:
The SLEEPDEEP bit of the SCR selects which sleep mode is used, see
ter” on page
Modes” in the PMC section of the datasheet.
This section describes the mechanisms for entering sleep mode, and the conditions for waking
up from sleep mode.
This section describes the mechanisms software can use to put the processor into sleep mode.
The system can generate spurious wakeup events, for example a debug operation wakes up the
processor. Therefore software must be able to put the processor back into sleep mode after
such an event. A program might have an idle loop to put the processor back to sleep mode.
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the proces-
sor executes a WFI instruction it stops executing instructions and enters sleep mode. See
on page 149
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of an
one-bit event register. When the processor executes a WFE instruction, it checks this register:
See
If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution of
an exception handler it returns to Thread mode and immediately enters sleep mode. Use this
mechanism in applications that only require the processor to run when an exception occurs.
The conditions for the processor to wakeup depend on the mechanism that cause it to enter
sleep mode.
Normally, the processor wakes up only when it detects an exception with sufficient priority to
cause exception entry.
Some embedded systems might have to execute system restore tasks after the processor
wakes up, and before it executes an interrupt handler. To achieve this set the PRIMASK bit to 1
and the FAULTMASK bit to 0. If an interrupt arrives that is enabled and has a higher priority than
current exception priority, the processor wakes up but does not execute the interrupt handler
• Backup Mode
• Wait Mode
• Sleep Mode
• if the register is 0 the processor stops executing instructions and enters sleep mode
• if the register is 1 the processor clears the register to 0 and continues executing instructions
without entering sleep mode.
“WFE” on page 148
173. For more information about the behavior of the sleep modes see “Low Power
for more information.
for more information.
SAM3S Preliminary
“System Control Regis-
“WFI”
73
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