ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 431
ATSAM3S4AA-MU
Manufacturer Part Number
ATSAM3S4AA-MU
Description
IC MCU 32BIT 256KB FLASH 48QFN
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4AA-MU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S4AA-MU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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26.5
26.6
26.7
6500C–ATARM–8-Feb-11
Processor Clock Controller
SysTick Clock
USB Clock Controller
Figure 26-2. Master Clock Controller
The PMC features a Processor Clock Controller (HCLK) that implements the Processor Sleep
Mode. The Processor Clock can be disabled by executing the WFI (WaitForInterrupt) or the
WFE (WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast Startup
Mode Register (PMC_FSMR).
The Processor Clock HCLK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Sleep Mode is achieved by disabling the Processor Clock,
which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the
product.
When Processor Sleep Mode is entered, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
The SysTick calibration value is fixed to 8000 which allows the generation of a time base of 1 ms
with SysTick clock to 8 MHz (max HCLK/8).
The user can select the PLLA or the PLLB output as the USB Source Clock by writing the USBS
bit in PMC_USB. If using the USB, the user must program the PLL to generate an appropriate
frequency depending on the USBDIV bit in PMC_USB.
When the PLL output is stable, i.e., the LOCK bit is set:
Figure 26-3. USB Clock Controller
• The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power
on this peripheral when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP
bit in PMC_SCSR gives the activity of this clock. The USB device port requires both the 48
MHz signal and the Master Clock. The Master Clock may be controlled via the Master Clock
Controller.
MAINCK
PLLACK
PLLBCK
SLCK
Source
Clock
USB
PMC_MCKR
CSS
/1,/2,/3,.../16
USBDIV
Divider
PMC_MCKR
Master Clock
Prescaler
PRES
UDP
SAM3S Preliminary
UDP Clock (UDPCK)
MCK
To the Processor
Clock Controller (PCK)
431
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