ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 765
ATSAM3S4AA-MU
Manufacturer Part Number
ATSAM3S4AA-MU
Description
IC MCU 32BIT 256KB FLASH 48QFN
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4AA-MU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S4AA-MU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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Figure 34-19. Quadrature Error Detection
34.6.14.4
6500C–ATARM–8-Feb-11
MCK
Abnormally formatted optical disk strips (theoretical view)
PHA
PHB
PHA
PHB
resulting PHA, PHB electrical waveforms
PHA
PHB
QERR
Even with an abnorrmaly formatted disk, there is no occurence of PHA, PHB switching at the same time.
Position and Rotation Measurement
A quadrature error is also reported by the quadrature decoder logic. Rather than reporting an
error only when 2 edges occur at the same time on PHA and PHB, which is unlikely to occur in
real life, there is a report if the time difference between 2 edges on PHA, PHB is lower than a
predefined value. This predefined value is configurable and corresponds to (MAXFILT+1) *
tMCK ns. After being filtered there is no reason to have 2 edges closer than (MAXFILT+1) *
tMCK ns under normal mode of operation. In the instance an anomaly occurs, a quadrature error
is reported on QERR flag on TC_QISR register.
MAXFILT must be tuned according to several factors such as the system clock frequency
(MCK), type of rotary sensor and rotation speed to be achieved.
When POSEN is set in TC_BMR register, position is processed on channel 0 (by means of the
PHA,PHB edge detections) and motor revolutions are accumulated in channel 1 timer/counter
and can be read through TC_CV0 and/or TC_CV1 register if the IDX signal is provided on
TIOA1 input.
Channel 0 and 1 must be configured in capture mode (WAVE = 0 in TC_CMR0).
strip edge inaccurary due to disk etching/printing process
duration < MAXFILT
MAXFILT = 2
SAM3S Preliminary
765
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