ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 499
ATSAM3S4AA-MU
Manufacturer Part Number
ATSAM3S4AA-MU
Description
IC MCU 32BIT 256KB FLASH 48QFN
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4AA-MU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S4AA-MU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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28.7
Table 28-3.
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Offset
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x005C
0x0060
0x0064
0x0068
0x006C
Parallel Input/Output Controller (PIO) User Interface
Register
PIO Enable Register
PIO Disable Register
PIO Status Register
Reserved
Output Enable Register
Output Disable Register
Output Status Register
Reserved
Glitch Input Filter Enable Register
Glitch Input Filter Disable Register
Glitch Input Filter Status Register
Reserved
Set Output Data Register
Clear Output Data Register
Output Data Status Register
Pin Data Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Interrupt Status Register
Multi-driver Enable Register
Multi-driver Disable Register
Multi-driver Status Register
Reserved
Pull-up Disable Register
Pull-up Enable Register
Pad Pull-up Status Register
Reserved
Register Mapping
Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Control-
ler User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined,
writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not mul-
tiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns
1 systematically.
(4)
Name
PIO_PER
PIO_PDR
PIO_PSR
PIO_OER
PIO_ODR
PIO_OSR
PIO_IFER
PIO_IFDR
PIO_IFSR
PIO_SODR
PIO_CODR
PIO_ODSR
PIO_PDSR
PIO_IER
PIO_IDR
PIO_IMR
PIO_ISR
PIO_MDER
PIO_MDDR
PIO_MDSR
PIO_PUDR
PIO_PUER
PIO_PUSR
SAM3S Preliminary
SAM3S Preliminary
Read-write
Read-only
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Access
or
(2)
0x0000 0000
0x0000 0000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
(1)
(3)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
499
499
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