ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 505
![IC MCU 32BIT 256KB FLASH 48QFN](/photos/7/34/73471/48-vqfn-6_543-5130_01-4_sml.jpg)
ATSAM3S4AA-MU
Manufacturer Part Number
ATSAM3S4AA-MU
Description
IC MCU 32BIT 256KB FLASH 48QFN
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4AA-MU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S4AA-MU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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28.7.7
Name:
Addresses:
Access:
This register can only be written if the WPEN bit is cleared in
• P0-P31: Input Filter Enable
0 = No effect.
1 = Enables the input glitch filter on the I/O line.
28.7.8
Name:
Addresses:
Access:
This register can only be written if the WPEN bit is cleared in
• P0-P31: Input Filter Disable
0 = No effect.
1 = Disables the input glitch filter on the I/O line.
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
P31
P23
P15
P31
P23
P15
P7
P7
31
23
15
31
23
15
7
7
PIO Input Filter Enable Register
PIO Input Filter Disable Register
P30
P22
P14
P30
P22
P14
P6
P6
30
22
14
30
22
14
PIO_IFER
0x400E0E20 (PIOA), 0x400E1020 (PIOB), 0x400E1220 (PIOC)
Write-only
6
PIO_IFDR
0x400E0E24 (PIOA), 0x400E1024 (PIOB), 0x400E1224 (PIOC)
Write-only
6
P29
P21
P13
P29
P21
P13
P5
P5
29
21
13
29
21
13
5
5
P28
P20
P12
P28
P20
P12
P4
P4
28
20
12
28
20
12
4
4
“PIO Write Protect Mode Register”
“PIO Write Protect Mode Register”
P27
P19
P11
P27
P19
P11
P3
P3
27
19
11
27
19
11
3
3
P26
P18
P10
P26
P18
P10
P2
P2
26
18
10
26
18
10
2
2
SAM3S Preliminary
SAM3S Preliminary
.
.
P25
P17
P25
P17
P9
P1
P9
P1
25
17
25
17
9
1
9
1
P24
P16
P24
P16
P8
P0
P8
P0
24
16
24
16
8
0
8
0
505
505
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