ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 534
ATSAM3S4AA-MU
Manufacturer Part Number
ATSAM3S4AA-MU
Description
IC MCU 32BIT 256KB FLASH 48QFN
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4AA-MU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S4AA-MU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 534 of 1118
- Download datasheet (24Mb)
28.7.53
Name:
Addresses:
Access:
• DRDY: Parallel Capture Mode Data Ready
0: No new data is ready to be read since the last read of PIO_PCRHR.
1: A new data is ready to be read since the last read of PIO_PCRHR.
The DRDY flag is automatically reset when PIO_PCRHR is read or when the parallel capture mode is disabled.
• OVRE: Parallel Capture Mode Overrun Error.
0 = No overrun error occurred since the last read of this register.
1 = At least one overrun error occurred since the last read of this register.
The OVRE flag is automatically reset when this register is read or when the parallel capture mode is disabled.
• ENDRX: End of Reception Transfer.
0 = The End of Transfer signal from the Reception PDC channel is inactive.
1 = The End of Transfer signal from the Reception PDC channel is active.
• RXBUFF: Reception Buffer Full
0: The signal Buffer Full from the Reception PDC channel is inactive.
1: The signal Buffer Full from the Reception PDC channel is active.
534
534
31
23
15
–
–
–
7
–
SAM3S Preliminary
SAM3S Preliminary
PIO Parallel Capture Interrupt Status Register
30
22
14
PIO_PCISR
0x400E0F60 (PIOA), 0x400E1160 (PIOB), 0x400E1360 (PIOC)
Read-only
–
–
–
6
–
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
RXBUFF
27
19
11
–
–
–
3
ENDRX
26
18
10
–
–
–
2
OVRE
25
17
–
–
–
9
1
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
DRDY
24
16
–
–
8
–
0
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