HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 168

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 3 Memory Management Unit (MMU)
3.3.4
In addition to the SH and SZ bits, the page management information of TLB entries also includes
D, C, and PR bits.
The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit
is 0, an attempt to write to the page results in an initial page write exception. For physical page
swapping between secondary memory and main memory, for example, pages are controlled so that
a dirty page is paged out of main memory only after that page is written back to secondary
memory. To record that there has been a write to a given page in the address translation table in
memory, an initial page write exception is used.
The C bit in the entry indicates whether the referenced page resides in a cacheable or non-
cacheable area of memory. When the control register in area 1 is mapped, set the C bit to 0.
The PR field specifies the access rights for the page in privileged and user modes and is used to
protect memory. Attempts at nonpermitted accesses result in TLB protection violation exceptions.
Access states designated by the D, C, and PR bits are shown in table 3.2.
Table 3.2
D bit
C bit
PR bit
Rev.6.00 Mar. 27, 2009 Page 110 of 1036
REJ09B0254-0600
Page Management Information
0
1
0
1
00
01
10
11
Access States Designated by D, C, and PR Bits
Reading
Permitted
Permitted
Permitted
(no caching)
Permitted
(with caching)
Permitted
Permitted
Permitted
Permitted
Privileged Mode
Initial page write
exception
Permitted
Permitted
(no caching)
Permitted
(with caching)
TLB protection
violation exception
Permitted
TLB protection
violation exception
Permitted
Writing
Permitted
Permitted
Permitted
(no caching)
Permitted
(with caching)
TLB protection
violation exception
TLB protection
violation exception
Permitted
Permitted
Reading
User Mode
Initial page write
Permitted
TLB protection
Permitted
Writing
exception
Permitted
(no caching)
Permitted
(with caching)
TLB protection
violation exception
TLB protection
violation exception
violation exception