HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 169

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

3.4
3.4.1
There are two kinds of MMU hardware management as follows:
1. The MMU decodes the logical address accessed by a process and performs address translation
2. In address translation, the MMU receives page management information and bit information
3.4.2
There are three kinds of MMU software management, as follows.
1. MMU register setting. MMUCR setting, in particular, should be performed in areas P1 and P2
2. TLB entry recording, deletion, and reading. TLB entry recording can be done in two ways by
3. MMU exception handling. When an MMU exception is generated, it is handled on the basis of
When single virtual memory mode is used, it is possible to create a state in which physical
memory access is enabled in the privileged mode only by clearing the share status bit (SH) to 0 to
specify recording of all TLB entries. This strengthens inter-process memory protection, and
enables special access levels to be created in the privileged mode only.
Recording a 1-kbyte page TLB entry may result in a synonym problem. See section 3.4.4,
Avoiding Synonym Problems.
by controlling the TLB in accordance with the MMUCR settings.
from the TLB, and determines the MMU exception and whether the cache is to be accessed
(using the C bit). For details of the determination method and the hardware processing, see
section 3.5, MMU Exceptions.
for which address translation is not performed. Also, since SV and IX bit changes constitute
address translation system changes, in this case, TLB flushing should be performed by
simultaneously writing 1 to the TF bit also. Since MMU exceptions are not generated in the
MMU disabled state with the AT bit cleared to 0, use in the disabled state must be avoided
with software that does not use the MMU.
using the LDTLB instruction, or by writing directly to the memory-mapped TLB. For TLB
entry deletion and reading, the memory allocation TLB can be accessed. See section 3.4.3,
MMU Instruction (LDTLB), for details of the LDTLB instruction, and section 3.6, Memory-
Mapped TLB, for details of the memory-mapped TLB.
information set from the hardware side. See section 3.5, MMU Exceptions, for details.
MMU Functions
MMU Hardware Management
MMU Software Management
Section 3 Memory Management Unit (MMU)
Rev.6.00 Mar. 27, 2009 Page 111 of 1036
REJ09B0254-0600