HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 689
![IC SUPERH MPU ROMLESS 240BGA](/photos/28/61/286131/240-lfbga__plbg0240ja-a_sml.jpg)
HD6417727BP100BV
Manufacturer Part Number
HD6417727BP100BV
Description
IC SUPERH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP100BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 689 of 1098
- Download datasheet (7Mb)
20.3.2
(1) SIOFSYNC
SIOFSYNC is the frame sync signal, and supports the two modes shown below.
• The pulse with 1 bit width which shows the first of the sync pulse frame.
• The pulse with 1/2 frame width, which shows left channel in L/R stereo data as high and right
Figure 20.3 shows synchronized timing as SIOFSYNC. Figure 20.3(a) shows the case for master
mode 1, slave mode 1, and slave mode 2. Figure 20.3(b) shows the case for master mode 2.
channel as low.
(a) At the synch pulse
(b) At the L/R
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
Serial Timing
1 bit delay
No delay
Figure 20.3 SIOF Serial Data Synchronized Timing
Lch. first bit data (MSB)
First bit data (MSB)
1/2 frame length
1 frame
1 frame
Rev.6.00 Mar. 27, 2009 Page 631 of 1036
Rch. first bit data (MSB)
1/2 frame length
Section 20 Serial IO (SIOF)
REJ09B0254-0600
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