HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 684

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 20 Serial IO (SIOF)
Bit 1—Receive FIFO Under Run Enable (RFUDRE)
Bit 1: RFUDRE
0
1
Bit 0—Receive FIFO Over Run Enable (RFOVRE)
Bit 0: RFOVRE
0
1
20.2.10 Transmit Data Register (SITDR)
This register sets transmit data to SIOF. The data that has been set to this register is stored in
transmit FIFO. This register is initialized at power on reset, software reset, or transmit reset.
Bits 31 to 16—Transmit Data for Left Channel (SITDL15 to SITDL0): These bits set data
transmitted from TXD_SIO as left channel data. The position for left channel side data are
assigned as TDLA bit of SITDA register.
This bit becomes effective when 1 is set to TDLE bit of SITDAR register.
Bits 15 to 0—Transmit Data for Right Channel (SITDR15 to SITDR0): These bits set data
transmitted from TXD_SIO as right channel data. The position for left channel side data are
assigned as TDRA bit of SITDA register.
This bit becomes effective when 1 is set to TDRE bit of SITDAR register, and 0 is set to TLREP
bit of SITDAR register.
Rev.6.00 Mar. 27, 2009 Page 626 of 1036
REJ09B0254-0600
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
SITDR
SITDL
31
15
15
15
W
W
0
0
SITDR
SITDL
30
14
14
14
W
W
0
0
Description
Disable interrupt of receive FIFO under run
Enable interrupt of receive FIFO under run (error interrupt)
Description
Disable interrupt of receive FIFO over run
Enable interrupt of receive FIFO over run (error interrupt)
SITDR
SITDL
29
13
13
13
W
W
0
0
SITDR
SITDL
28
12
12
12
W
W
0
0
SITDR
SITDL
27
11
11
11
W
W
0
0
SITDR
SITDL
26
10
10
10
W
W
0
0
SITDR
SITDL
25
W
W
9
0
9
9
0
SITDR
SITDL
24
W
W
8
0
8
8
0
SITDR
SITDL
23
W
W
7
0
7
7
0
SITDR
SITDL
22
W
W
6
0
6
6
0
SITDR
SITDL
21
W
W
5
0
5
5
0
SITDR
SITDL
20
W
W
4
0
4
4
0
SITDR
SITDL
19
W
W
3
0
3
3
0
SITDR
SITDL
18
W
W
2
0
2
2
0
SITDR
SITDL
17
W
W
1
0
1
1
0
SITDR
SITDL
16
W
W
0
0
0
0
0