HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 287

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

5. Register specifications
6. Register specifications
BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000,
BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300001, BETR = H'0005
Specified conditions: Channel A/channel B independent mode
•
•
On channel A, a user break occurs before an instruction of address H'00000500 is executed.
On channel B, a user break occurs before the fifth instruction execution after instructions of
address H'00001000 are executed four times.
BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010,
BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000400, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
•
•
A user break occurs after an instruction with ASID = H'80 and address H'00008000 to
H'00008FFE is executed or before instructions with ASID = H'70 and addresses H'00008010
to H'00008016 are executed.
Address:
Bus cycle: CPU/instruction fetch (before instruction execution)/read/longword
Address:
Data:
Bus cycle: CPU/instruction fetch (before instruction execution)/read/longword
The number of execution-times break enable (5 times)
Address:
Bus cycle: CPU/instruction fetch (after instruction execution)/read (operand size is not
Address:
Data:
Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not
Channel A
Channel B
Channel A
Channel B
H'00000500, Address mask: H'00000000
H'00001000, Address mask: H'00000000
H'00000000, Data mask: H'00000000
H'00008404, Address mask: H'00000FFF, ASID: H'80
included in the condition)
H'00008010, Address mask: H'00000006, ASID: H'70
H'00000000, Data mask: H'00000000
included in the condition)
Rev.6.00 Mar. 27, 2009 Page 229 of 1036
Section 8 User Break Controller
REJ09B0254-0600