HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 835

IC SUPERH MPU ROMLESS 240BGA

HD6417727BP100BV

Manufacturer Part Number
HD6417727BP100BV
Description
IC SUPERH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727BP100BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
25.2.8
LDPALCR selects whether the CPU or LCDC accesses the palette memory. When the palette
memory is being used for display operation, display mode should be selected. When the palette
memory is being written to, CPU access mode should be selected.
Bits 15 to 5 and 3 to 1—Reserved
Bit 4—Palette State (PALS): Indicates the access right state of the palette.
Bit 4
PALS
0
1
Bit 0—Palette Read/Write Enable (PALEN): Controls CPU accesses to the palette.
Bit 0
PALEN
0
1
Initial value:
R/W:
Bit:
LCDC Palette Control Register (LDPALCR)
15
R
0
Description
Description
Display mode: LCDC uses the palette
CPU access mode: The host (CPU) uses the palette
Display mode: LCDC uses the palette
CPU access mode: The host (CPU) uses the palette
14
R
0
13
R
0
12
R
0
11
R
0
10
R
0
R
9
0
R
8
0
Rev.6.00 Mar. 27, 2009 Page 777 of 1036
R
0
7
R
6
0
R
5
0
Section 25 LCD Controller
PALS
R
4
0
R
3
0
REJ09B0254-0600
R
2
0
(Initial value)
(Initial value)
R
1
0
PALEN
R/W
0
0

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