HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 272

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 User Break Controller
Bits 5 and 4—Instruction Fetch/Data Access Select B (IDB1 and IDB0): Select the instruction
fetch cycle or data access cycle as the bus cycle of the channel B break condition.
Bit 5: IDB1
0
1
Bits 3 and 2—Read/Write Select B (RWB1 and RWB0): Select the read cycle or write cycle as
the bus cycle of the channel B break condition.
Bit 3: RWB1
0
1
Bits 1 and 0—Operand Size Select B (SZB1 and SZB0): Select the operand size of the bus
cycle for the channel B break condition.
Bit 1: SZB1
0
1
Rev.6.00 Mar. 27, 2009 Page 214 of 1036
REJ09B0254-0600
Bit 4: IDB0
0
1
0
1
Bit 2: RWB0
0
1
0
1
Bit 0: SZB0
0
1
0
1
Description
Condition comparison is not performed
The break condition is the instruction fetch cycle
The break condition is the data access cycle
The break condition is the instruction fetch cycle or data access
cycle
Description
Condition comparison is not performed
The break condition is the read cycle
The break condition is the write cycle
The break condition is the read cycle or write cycle
Description
The break condition does not include operand size (Initial value)
The break condition is byte access
The break condition is word access
The break condition is longword access
(Initial value)
(Initial value)