HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 227

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

7.2
There are five types of interrupt sources: NMI, IRQ, IRL, PINT, and on-chip supporting modules.
Each interrupt has priority levels (0 to 16) with 0 the lowest and 16 the highest. Priority level 0
masks an interrupt.
7.2.1
The NMI interrupt has the highest priority level of 16. When the BLMSK bit of the interrupt
control register (ICR1) is 1 or the BL bit of the status register (SR) is 0, NMI interrupts are
accepted when the MAI bit of the ICR1 register is 0. NMI interrupts are edge-detected. In sleep or
standby mode, the interrupt is accepted regardless of the BL. The NMI edge select bit (NMIE) in
the interrupt control register 0 (ICR0) is used to select either the rising or falling edge. When the
NMIE bit of the ICR0 register is changed, the NMI interrupt is not detected for 20 cycles after
changing the ICR0.NMIE to avoid a false detection of the NMI interrupt. NMI interrupt exception
handling does not affect the interrupt mask level bits (I3 to I0) in the status register (SR).
When the BLMSK bit of the ICR1 register is set to 1 and only NMI interrupts are accepted, the
SPC register and SSR register are updated by the NMI interrupt handler, making it impossible to
return to the original processing from exception handling initiated prior to the NMI. Use should
therefore be restricted to cases where return is not necessary.
It is possible to wake the chip up from the standby state with an NMI interrupt (except when the
MAI bit of the ICR1 register is set to 1).
7.2.2
IRQ interrupts are input by priority from pins IRQ0 to IRQ5 with a level or an edge. The priority
level can be set by priority setting registers C, D (IPRC, IPRD) in a range from levels 0 to 15.
When using edge sensing for IRQ interrupts, do the following to clear IR0.
To clear bits IRQ5R to IRQ0R to 0, read from IRR0 before writing. After confirming that the bits
to be cleared to 0 are set to 1, write 0 to them. In this case write 0 only to the bits to be cleared;
write 1 to the other bits. The values of the bits to which 1 is written do not change.
When level sensing is used for IRQ interrupts, bits IRQ5R to IRQ0R indicate whether or not an
interrupt request has been input. They can be set and cleared by the values input to pins IRQ5R to
IRQ0R alone.
Interrupt Sources
NMI Interrupts
IRQ Interrupt
Rev.6.00 Mar. 27, 2009 Page 169 of 1036
Section 7 Interrupt Controller (INTC)
REJ09B0254-0600