HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 774
![IC SUPERH MPU ROMLESS 240BGA](/photos/28/61/286131/240-lfbga__plbg0240ja-a_sml.jpg)
HD6417727BP100BV
Manufacturer Part Number
HD6417727BP100BV
Description
IC SUPERH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP100BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Section 23 USB Function Controller
23.6.6
Rev.6.00 Mar. 27, 2009 Page 716 of 1036
REJ09B0254-0600
Note: This flow is an example of interrupt transfer processing. When there is data to be transferred, the
following flow can also be considered.
"Confirm that FIFO is empty by referring to the EP3 DE bit of the USB data status register and write
data to FIFO."
EP3 Interrupt-In Transfer
Data transmission to host
Set EP3 transfer-end flag
(USBIFR1/EP3 TS = 1)
IN token reception
IN token reception
USB function
in EP3 FIFO?
Valid data
Figure 23.12 EP2 Interrupt-In Transfer Operation
Yes
ACK
NACK
No
Clear EP3 transfer-end flag
Clear EP3 transfer-request
(USBTRG/EP3 PKTE = 1)
(USBTRG/EP3 PKTE = 1)
(USBIFR1/EP3 TR = 0)
(USBIFR1/EP3 TS = 0)
Write data to USBEP3
Write data to USBEP3
Write to EP3 packet
Write to EP3 packet
data register
data register
enable bit
enable bit
flag
Application
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