HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet
HD64F3048VTF8
Specifications of HD64F3048VTF8
Related parts for HD64F3048VTF8
HD64F3048VTF8 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8/3048 Group, 16 H8/3048 F-ZTAT Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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The H8/3048 Group is a series of high-performance microcontrollers that integrate system supporting functions together with an H8/300H CPU core. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed ...
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Rev. 7.00 Sep 21, 2005 page iv of xxiv ...
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Comparison of H8/3048 Group Product Specifications There are seven members of the H8/3048 Group; the H8/3048F-ZTAT (H8/3048F * ONE * 2 ), H8/3048ZTAT, H8/3048 mask ROM version, H8/3047 mask ROM version, H8/3045 mask ROM version, and H8/3044 mask ROM version. ...
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Hardware Manual ROM Type ZTAT ROM Capacity 128 kbytes Flash Memory — Clock Pulse Refer to section 20, Clock Pulse Generator. Generator Power-Down Refer to section 21, Power-Down State. State Clock oscillator settling time: Waiting time 131072 ...
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Main Revisions for this Edition Item Page All 13.2.6 Serial Control 461 Register (SCR) Bit 6-Receive Interrupt Enable (RIE) 19.5.3 Programming 606 Flowchart and Sample Program Flowchart for Programming One Byte Figure 19.9 Programming Flowchart Revision (See Manual for Details) ...
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Item Page 19.5.6 Erasing 610 Flowchart and Sample Program Flowchart for Erasing One Block Figure 19.10 Erasing Flowchart Rev. 7.00 Sep 21, 2005 page viii of xxiv Revision (See Manual for Details) Figure amended Set top address in block as ...
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Item Page 19.5.6 Erasing 611 Flowchart and Sample Program Prewrite Flowchart Figure 19.11 Prewrite Flowchart Revision (See Manual for Details) Figure amended Write H'00 to flash memory (flash memory latches *1 write address and write data) Enable watchdog timer *2 ...
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Item Page 19.5.6 Erasing 616 Flowchart and Sample Program Flowchart for Erasing Multiple Blocks Figure 19.12 Multiple-Block Erase Flowchart Rev. 7.00 Sep 21, 2005 page x of xxiv Revision (See Manual for Details) Figure amended Wait initial value setting x ...
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Section 1 Overview ........................................................................................................... 1.1 Overview........................................................................................................................... 1.2 Block Diagram .................................................................................................................. 1.3 Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Assignments in Each Mode ........................................................................... 10 1.3.3 Pin Functions ....................................................................................................... 15 1.4 Differences between H8/3048F and H8/3048F-ONE ....................................................... 20 Section 2 ...
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Bus-Released State............................................................................................... 60 2.8.6 Reset State............................................................................................................ 60 2.8.7 Power-Down State ............................................................................................... 60 2.9 Basic Operational Timing ................................................................................................. 61 2.9.1 Overview.............................................................................................................. 61 2.9.2 On-Chip Memory Access Timing........................................................................ 61 2.9.3 On-Chip Supporting Module Access Timing....................................................... 62 2.9.4 Access to External Address ...
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Section 5 Interrupt Controller 5.1 Overview........................................................................................................................... 91 5.1.1 Features ................................................................................................................ 91 5.1.2 Block Diagram ..................................................................................................... 92 5.1.3 Pin Configuration................................................................................................. 93 5.1.4 Register Configuration......................................................................................... 93 5.2 Register Descriptions ........................................................................................................ 94 5.2.1 System Control Register (SYSCR) ...................................................................... 94 5.2.2 Interrupt Priority Registers ...
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Operation .......................................................................................................................... 133 6.3.1 Area Division....................................................................................................... 133 6.3.2 Chip Select Signals .............................................................................................. 134 6.3.3 Data Bus............................................................................................................... 136 6.3.4 Bus Control Signal Timing .................................................................................. 137 6.3.5 Wait Modes.......................................................................................................... 145 6.3.6 Interconnections with Memory (Example) .......................................................... 151 6.3.7 Bus Arbiter Operation.......................................................................................... ...
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Register Descriptions (Short Address Mode).................................................................... 203 8.2.1 Memory Address Registers (MAR) ..................................................................... 203 8.2.2 I/O Address Registers (IOAR) ............................................................................. 204 8.2.3 Execute Transfer Count Registers (ETCR) .......................................................... 205 8.2.4 Data Transfer Control Registers (DTCR) ............................................................ 206 8.3 Register Descriptions ...
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Register Descriptions ........................................................................................... 262 9.3 Port 2................................................................................................................................. 264 9.3.1 Overview.............................................................................................................. 264 9.3.2 Register Descriptions ........................................................................................... 265 9.4 Port 3................................................................................................................................. 268 9.4.1 Overview.............................................................................................................. 268 9.4.2 Register Descriptions ........................................................................................... 268 9.5 Port 4................................................................................................................................. 270 9.5.1 Overview.............................................................................................................. 270 9.5.2 Register Descriptions ........................................................................................... ...
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Register Descriptions ........................................................................................................ 327 10.2.1 Timer Start Register (TSTR)................................................................................ 327 10.2.2 Timer Synchro Register (TSNC) ......................................................................... 328 10.2.3 Timer Mode Register (TMDR) ............................................................................ 330 10.2.4 Timer Function Control Register (TFCR)............................................................ 333 10.2.5 Timer Output Master Enable Register (TOER) ................................................... ...
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Port A Data Direction Register (PADDR) ........................................................... 415 11.2.2 Port A Data Register (PADR).............................................................................. 415 11.2.3 Port B Data Direction Register (PBDDR) ........................................................... 416 11.2.4 Port B Data Register (PBDR) .............................................................................. 416 11.2.5 Next Data Register A (NDRA) ............................................................................ ...
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Section 13 Serial Communication Interface 13.1 Overview........................................................................................................................... 451 13.1.1 Features ................................................................................................................ 451 13.1.2 Block Diagram ..................................................................................................... 453 13.1.3 Input/Output Pins ................................................................................................. 454 13.1.4 Register Configuration......................................................................................... 454 13.2 Register Descriptions ........................................................................................................ 455 13.2.1 Receive Shift Register (RSR)............................................................................... 455 13.2.2 Receive Data ...
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Transmitting and Receiving Data ........................................................................ 524 14.4 Usage Notes ...................................................................................................................... 531 Section 15 A/D Converter 15.1 Overview........................................................................................................................... 535 15.1.1 Features................................................................................................................ 535 15.1.2 Block Diagram..................................................................................................... 536 15.1.3 Input Pins ............................................................................................................. 537 15.1.4 Register Configuration......................................................................................... 538 15.2 Register Descriptions ........................................................................................................ 539 ...
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System Control Register (SYSCR) ................................................................................... 567 17.3 Operation........................................................................................................................... 568 Section 18 ROM (H8/3048ZTAT and Mask-ROM Versions) 18.1 Overview........................................................................................................................... 569 18.1.1 Block Diagram ..................................................................................................... 570 18.2 PROM Mode..................................................................................................................... 571 18.2.1 PROM Mode Setting............................................................................................ 571 18.2.2 Socket Adapter and Memory Map ...
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Protect Modes ...................................................................................................... 625 19.5.9 NMI Input Masking ............................................................................................. 628 19.6 Flash Memory Emulation by RAM................................................................................... 629 19.7 Flash Memory PROM Mode............................................................................................. 631 19.7.1 PROM Mode Setting............................................................................................ 631 19.7.2 Socket Adapter and Memory Map ....................................................................... 632 19.7.3 Operation in ...
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Exit from Hardware Standby Mode ..................................................................... 673 21.5.3 Timing for Hardware Standby Mode ................................................................... 673 21.6 Module Standby Function ................................................................................................. 674 21.6.1 Module Standby Timing ...................................................................................... 674 21.6.2 Read/Write in Module Standby............................................................................ 674 21.6.3 Usage Notes ......................................................................................................... 675 21.7 ...
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B.2 Function ............................................................................................................................ 764 Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram ....................................................................................................... 844 C.2 Port 2 Block Diagram ....................................................................................................... 845 C.3 Port 3 Block Diagram ....................................................................................................... 846 C.4 Port 4 Block Diagram ....................................................................................................... 847 C.5 Port ...
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Overview The H8/3048 Group is a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Renesas Technology architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general ...
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Section 1 Overview Table 1.1 Features Feature Description CPU Upward-compatible with the H8/300 CPU at the object-code level General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers + eight 16-bit registers or eight 32- bit registers) High-speed ...
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Feature Description Memory H8/3048, H8/3048F ROM: 128 kbytes RAM: 4 kbytes H8/3047 ROM: 96 kbytes RAM: 4 kbytes H8/3045 ROM: 64 kbytes RAM: 2 kbytes H8/3044 ROM: 32 kbytes RAM: 2 kbytes Interrupt Seven external interrupt pins: NMI, IRQ0 to ...
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Section 1 Overview Feature Description DMA controller Short address mode (DMAC) Maximum four channels available Selection of I/O mode, idle mode, or repeat mode Can be activated by compare match/input capture A interrupts from ITU channels transmit-data-empty ...
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Feature Description Serial Selection of asynchronous or synchronous mode communication Full duplex: can transmit and receive simultaneously interface (SCI), On-chip baud-rate generator 2 channels Smart card interface functions added (SCI0 only) A/D converter Resolution: 10 bits Eight channels, with selection ...
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Section 1 Overview Feature Description Other features On-chip clock pulse generator Product lineup Model (5 V) HD64F3048TF HD64F3048F HD6473048TF HD6473048F HD6433048TF HD6433048F HD6433047TF HD6433047F HD6433045TF HD6433045F HD6433044TF HD6433044F Rev. 7.00 Sep 21, 2005 page 6 of 878 REJ09B0259-0700 Model (3 ...
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Block Diagram Figure 1.1 shows an internal block diagram EXTAL XTAL STBY RES /RESO * V PP NMI P6 /LWR 6 P6 /HWR /BACK 2 ...
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Section 1 Overview 1.3 Pin Description 1.3.1 Pin Arrangement Figure 1.2 shows the pin arrangement of the H8/3048 Group. The pin arrangement of the H8/3048 Group is shown in figure 1.2. Differences in the H8/3048 Group pin arrangements are shown ...
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REF /AN /DA 84 ...
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Section 1 Overview 1.3.2 Pin Assignments in Each Mode Table 1.3 lists the pin assignments in each mode. Table 1.3 Pin Assignments in Each Mode (FP-100B or TFP-100B) Pin No. Mode 1 Mode 2 Mode ...
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Pin Mode 1 Mode 2 Mode 3 No. RESO RESO RESO /TxD P9 /TxD P9 /TxD /TxD P9 /TxD P9 /TxD ...
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Section 1 Overview Pin Mode 1 Mode 2 Mode 3 No ...
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Pin Mode 1 Mode 2 Mode 3 No REF REF REF 78 P7 /AN P7 / /AN P7 /AN P7 ...
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Section 1 Overview Pin Mode 1 Mode 2 Mode TIOCA / TIOCA / TIOCA ...
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Pin Functions Table 1.4 summarizes the pin functions. Table 1.4 Pin Functions Type Symbol Power Clock XTAL EXTAL Operating mode control Pin No. I/O Name and Function 1, 35, 68 ...
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Section 1 Overview Type Symbol RES System control RESO (RESO STBY BREQ BACK Interrupts NMI IRQ to 5 IRQ 0 Address bus Data bus Bus ...
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Type Symbol RFSH Refresh controller HWR LWR DREQ DMA controller , 1 DREQ (DMAC) 0 TEND , 1 TEND 0 16-bit integrated TCLKD to timer unit (ITU) TCLKA TIOCA to 4 TIOCA 0 TIOCB to 4 TIOCB ...
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Section 1 Overview Type Symbol Programmable timing pattern controller (TPC) Serial TxD , TxD 1 0 communication interface (SCI) RxD , RxD 1 0 SCK , SCK 1 0 A/D converter ...
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Type Symbol I/O ports Pin No. I/O Name and Function ...
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Section 1 Overview 1.4 Differences between H8/3048F and H8/3048F-ONE Table 1.5 shows the differences between the H8/3048F (dual power supply model) and H8/3048F- ONE (single power supply model). Table 1.5 Differences between H8/3048F and H8/3048F-ONE Models with Dual Power Supply: ...
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Models with Dual Power Supply: H8/3048F Item Write Before writing, sets the block with the processing address to be written to EBR1/EBR2 FLMCR FLMCR (H'FF40 — EBR EBR1 (H'FF42) LB7 LB6 LB5 LB4 LB3 LB2 ...
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Section 1 Overview Models with Dual Power Supply: Item H8/3048F Division of RAM On-chip RAM emulation block H'EF10 H'F000 H'F1FF H'FF0F Reset during The RES signal must be kept low during operation at least 6 system clock (6 ) cycles. ...
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Models with Dual Power Supply: H8/3048F Item Clock oscillator Setting of standby timer select settling time bits (SYSCR STS2– STS2 STS1 STS0 Details on flash Refer to section 19, Flash Memory ...
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Section 1 Overview Rev. 7.00 Sep 21, 2005 page 24 of 878 REJ09B0259-0700 ...
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Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 2 CPU 18 MHz (H8/3048ZTAT, H8/3048 mask ROM, H8/3047 mask ROM, H8/3045 mask ROM, H8/3044 mask ROM) 16 MHz (H8/3048F) 8/16/32-bit register-register add/subtract: 111 MHz/125 MHz 8 8-bit register-register multiply: 16 ÷ 8-bit ...
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CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports Mbytes. See figure 2.1. The H8/3048 Group can be used only in ...
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Section 2 CPU 2.3 Address Space The maximum address space of the H8/300H CPU is 16 Mbytes. The H8/3048 Group has various operating modes (MCU modes), some providing a 1-Mbyte address space, the others supporting the full 16 Mbytes. Figure ...
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Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. Figure 2.3 CPU Internal Registers Rev. 7.00 Sep 21, 2005 page 29 of ...
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Section 2 CPU 2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as ...
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General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack. SP (ER7) 2.4.3 Control Registers The control registers are ...
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Section 2 CPU When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4—User Bit (U): Can ...
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Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
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Section 2 CPU General Data Type Register Data Format Word data Rn 15 Word data En MSB 31 Longword data ERn MSB Legend ERn: General register En: General register E Rn: General register R RnH: General register RH RnL: General ...
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Memory Data Formats Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address attempt is made ...
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Section 2 CPU 2.6 Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified in table 2.1. Table 2.1 Instruction Classification Function Instruction MOV, PUSH * Data transfer Arithmetic operatiozns ADD, SUB, ADDX, ...
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Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Function Instruction Data MOV BWL transfer POP, PUSH — MOVFPE*, — MOVTPE* Arithmetic ADD, CMP BWL operations SUB WL ...
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Section 2 CPU Note: * Not availabe in the H8/3048 Group. 2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation ...
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Table 2.3 Data Transfer Instructions Instruction Size* MOV B/W/L MOVFPE B MOVTPE B POP W/L PUSH W/L Note: * Size refers to the operand size. B: Byte W: Word L: Longword Function (EAs) Rd, Rs (EAd) Moves data between two ...
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Section 2 CPU Table 2.4 Arithmetic Operation Instructions Instruction Size* ADD, SUB B/W/L ADDX, SUBX B INC, DEC B/W/L ADDS, SUBS L DAA, DAS B MULXU B/W MULXS B/W Note: * Size refers to the operand size. B: Byte W: ...
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Instruction Size* DIVXU B/W DIVXS B/W CMP B/W/L NEG B/W/L EXTS W/L EXTU W/L Note: * Size refers to the operand size. B: Byte W: Word L: Longword Function Rd ÷ Performs unsigned division on data in two ...
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Section 2 CPU Table 2.5 Logic Operation Instructions Instruction Size* AND B/W/L OR B/W/L XOR B/W/L NOT B/W/L Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Shift Instructions Instruction Size* SHAL, B/W/L ...
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Table 2.7 Bit Manipulation Instructions Instruction Size* BSET B BCLR B BNOT B BTST B BAND B BIAND B Note: * Size refers to the operand size. B: Byte Function 1 (<bit-No.> of <EAd>) Sets a specified bit in a ...
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Section 2 CPU Instruction Size* BOR B BIOR B BXOR B BIXOR B BLD B BILD B BST B BIST B Note: * Size refers to the operand size. B: Byte Rev. 7.00 Sep 21, 2005 page 44 of 878 ...
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Table 2.8 Branching Instructions Instruction Size Bcc — JMP — BSR — JSR — RTS — Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description BRA (BT) Always (true) ...
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Section 2 CPU Table 2.9 System Control Instructions Instruction Size* TRAPA — RTE — SLEEP — LDC B/W STC B/W ANDC B ORC B XORC B NOP — Note: * Size refers to the operand size. B: Byte W: Word ...
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Table 2.10 Block Transfer Instruction Instruction Size EEPMOV.B — EEPMOV.W — 2.6.4 Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address ...
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Section 2 CPU Figure 2.9 shows examples of instruction formats. Operation field only Operation field and register fields op Operation field, register fields, and effective address extension op Operation field, effective address extension, and condition field op cc 2.6.5 Notes ...
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are set as output pins, and are in the low-level output state this example, the BCLR instruction is used to make P4 Before Execution of BCLR Instruction Input/output Input Input DDR ...
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Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use ...
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Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the ...
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Section 2 CPU 7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign- extended to 24 bits and added to the ...
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Table 2.13 Effective Address Calculation Addressing Mode and No. Instruction Format 1 Register direct (Rn Register indirect (@ERn Register indirect with displacement @(d:16, ERn)/@(d:24, ERn disp 4. Register indirect with post-increment ...
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Section 2 CPU Addressing Mode and Instruction Format No. 5 Absolute address @aa:8 @aa:8 op abs @aa:16 op abs @aa:24 op abs 6 Immediate #xx:8, #xx:16, or #xx:32 op IMM 7 Program-counter relative @(d:8, PC) or @(d:16, PC) op disp ...
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Addressing Mode and Instruction Format No. 8 Memory indirect @@aa:8 Normal mode op abs Advanced mode op abs Legend: r, rm, rn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: Absolute address Effective Address Calculation 23 8 ...
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Section 2 CPU 2.8 Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby ...
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Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, ...
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Section 2 CPU Reset Exception Interrupt sources Trap instruction Figure 2.12 Classification of Exception Sources End of bus release Bus-released state End of exception handling Exception-handling state RES = 1 *1 Reset state Notes: 1. From any state except hardware ...
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Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception ...
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Section 2 CPU 2.8.5 Bus-Released State In this state the bus is released to a bus master other than the CPU, in response to a bus request. The bus masters other than the CPU are the DMA controller, the refresh ...
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Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock ( ). The interval from one rise of the system clock to the next rise is referred “state.” A memory cycle or ...
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Section 2 CPU Address bus , , , Figure 2.16 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus is ...
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Address bus , , , Figure 2.18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas 0 to 7). Bus-controller ...
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Section 2 CPU Rev. 7.00 Sep 21, 2005 page 64 of 878 REJ09B0259-0700 ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8/3048 Group has seven operating modes (modes that are selected by the mode pins ( indicated in table 3.1. The input ...
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Section 3 MCU Operating Modes Modes 5 and 6 are externally expanded modes that enable access to external memory and peripheral devices and also enable access to the on-chip ROM. Mode 5 supports a maximum address space of 1 Mbyte. ...
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Bits 2 to 0—Mode Select (MDS2 to MDS0): These bits indicate the logic levels at pins (the current operating mode). MDS2 to MDS0 correspond MDS0 are read-only bits. The mode ...
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Section 3 MCU Operating Modes Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is ...
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Operating Mode Descriptions 3.4.1 Mode 1 Ports 1, 2, and 5 function as address pins A address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas least one area ...
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Section 3 MCU Operating Modes 3.4.6 Mode 6 Ports 1, 2, and 5 and part of port A function as address pins A maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2, ...
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Memory Map in Each Operating Mode Figure 3.1 shows a memory map of the H8/3048. Figure 3.2 shows a memory map of the H8/3047. Figure 3.3 shows a memory map of the H8/3044. Figure 3.4 shows a memory map ...
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Section 3 MCU Operating Modes Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'F8000 H'FEF0F ...
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Mode 5 (1-Mbyte expanded mode with on-chip ROM enabled) H'00000 Vector area H'000FF On-chip ROM H'07FFF Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External address Area 3 space H'7FFFF H'80000 Area 4 H'9FFFF H'A0000 Area ...
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Section 3 MCU Operating Modes Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address H'7FFFF space H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'F8000 H'FEF0F ...
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Mode 5 (1-Mbyte expanded mode with on-chip ROM enabled) H'00000 Vector area H'000FF On-chip ROM H'07FFF H'17FFF H'18000 Reserved *1 Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External address Area 3 space H'7FFFF H'80000 Area ...
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Section 3 MCU Operating Modes Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'F8000 H'FEF10 ...
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Mode 5 (1-Mbyte expanded mode with on-chip ROM enabled) H'00000 Vector area H'000FF On-chip ROM H'07FFF H'08000 *1 Reserved Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External address Area 3 space H'7FFFF H'80000 Area 4 ...
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Section 3 MCU Operating Modes Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'F8000 H'FEF10 ...
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Mode 5 (1-Mbyte expanded mode with on-chip ROM enabled) H'00000 Vector area H'000FF On-chip ROM H'07FFF H'0FFFF H'10000 *1 Reserved Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External address Area 3 H'7FFFF space H'80000 Area ...
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Section 3 MCU Operating Modes Rev. 7.00 Sep 21, 2005 page 80 of 878 REJ09B0259-0700 ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset Exception • ...
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Table 4.2 Exception Vector Table Exception Source Reset Reserved for system use External interrupt (NMI) Trap instruction (4 sources) External interrupt IRQ 0 External interrupt IRQ 1 External interrupt IRQ 2 External interrupt IRQ 3 External interrupt IRQ 4 External ...
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Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and ...
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Figure 4.2 Reset Sequence (Modes 1 and 3) Section 4 Exception Handling Rev. 7.00 Sep 21, 2005 page 85 of 878 REJ09B0259-0700 ...
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Section 4 Exception Handling RES Address bus RD HWR LWR , High (1), (3) Address of reset vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset vector) (5) Start address ...
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RES Internal address bus Internal read signal Internal write signal Internal data bus (16 bits wide) (1), (3) Address of reset vector ((1) = H'000000, (2) = H'000002) (2), (4) Start address (contents of reset vector) (5) Start address (6) ...
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Section 4 Exception Handling 4.3 Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ 30 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt sources and indicates the number of interrupts of each ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set the system control register (SYSCR), the exception handling sequence sets the I bit CCR. ...
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Section 4 Exception Handling 4.6 Notes on Stack Usage When accessing word data or longword data, the H8/3048 Group regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt ...
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Section 5 Interrupt Controller 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR NMI input IRQ input OVF TME . . . . . . . . . . ADI ADIE Interrupt controller Legend ISCR: ...
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Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Nonmaskable interrupt External interrupt request 5.1.4 Register Configuration Table 5.2 lists the registers of the interrupt controller. Table 5.2 Interrupt Controller Registers 1 ...
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Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables ...
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Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3: UE Description 0 UI bit in CCR is used as interrupt mask bit 1 UI ...
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Section 5 Interrupt Controller Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRA7 IPRA6 Initial value 0 Read/Write R/W R/W Priority level A6 Selects the priority level ...
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Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ Bit 7: IPRA7 Description 0 IRQ interrupt requests have priority level 0 (low priority IRQ interrupt requests have priority level 1 (high priority) 0 Bit 6—Priority Level ...
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Section 5 Interrupt Controller Bit 2—Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests. Bit 2: IPRA2 Description 0 ITU channel 0 interrupt requests have priority level 0 (low priority) (Initial value) 1 ITU channel ...
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Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRB7 IPRB6 Initial value 0 Read/Write R/W R/W Priority level B6 Selects the priority level of ITU channel 4 ...
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Section 5 Interrupt Controller Bit 7—Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests. Bit 7: IPRB7 Description 0 ITU channel 3 interrupt requests have priority level 0 (low priority) (Initial value) 1 ITU channel ...
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Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests. Bit 3: IPRB3 Description 0 SCI0 interrupt requests have priority level 0 (low priority) 1 SCI0 interrupt requests have priority level 1 (high priority) Bit ...
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Section 5 Interrupt Controller 5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ requests. Bit 7 — Initial value 0 Read/Write — Reserved bits Note: Only 0 can be written, to clear ...
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IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ Bit 7 — — Initial value 0 Read/Write R/W R/W Reserved bits IER is initialized to H' reset and in hardware standby ...
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Section 5 Interrupt Controller 5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ to IRQ . 5 0 Bit 7 — Initial value 0 ...
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Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ can be used to exit software standby mode. NMI: NMI is the highest-priority interrupt and is always accepted, ...
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Section 5 Interrupt Controller Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). IRQn input pin IRQnF Note Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector ...
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Table 5.3 Interrupt Sources, Vector Addresses, and Priority Interrupt Source Origin NMI External pins IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 Reserved — WOVI Watchdog (interval timer) timer CMI Refresh (compare match) controller Reserved — ...
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Section 5 Interrupt Controller Interrupt Source Origin IMIA2 ITU channel 2 (compare match/ input capture A2) IMIB2 (compare match/ input capture B2) OVI2 (overflow 2) Reserved — IMIA3 ITU channel 3 (compare match/ input capture A3) IMIB3 (compare match/ input ...
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Interrupt Source Origin ERI0 SCI channel 0 (receive error 0) RXI0 (receive data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) ERI1 SCI channel 1 (receive error 1) RXI1 (receive data full 1) TXI1 (transmit data empty ...
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Section 5 Interrupt Controller 5.4 Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3048 Group handles interrupts differently depending on the setting of the UE bit. When interrupts are controlled by the I bit. When ...
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Program execution state Interrupt requested? Yes Priority level 1? Yes No IRQ 0 Yes No IRQ 1 Yes ADI Yes Save PC and CCR Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance when ...
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Section 5 Interrupt Controller If an interrupt condition occurs and the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. When the interrupt controller receives one or more interrupt requests, it selects ...
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All interrupts are unmasked I 0 Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5 flowchart showing how interrupts are accepted when interrupt condition occurs and the corresponding interrupt enable bit is ...
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Section 5 Interrupt Controller Priority level 1? IRQ 0 Yes IRQ Figure 5.6 Process Up to Interrupt Acceptance when Rev. 7.00 Sep 21, 2005 page 114 of 878 REJ09B0259-0700 Program execution state Interrupt requested? ...
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Interrupt Sequence Figure 5.7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5.7 Interrupt Sequence (Mode 2, Two-State Access, ...
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Section 5 Interrupt Controller 5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time No. Item ...
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Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed interrupt ...
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Section 5 Interrupt Controller 5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing ...
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Occurrence conditions 1. When IRQaF = 1, for the IRQaF flag to clear, ISR register read is executed. Thereafter interrupt processing is carried out and IRQbF flag clears. 2. IRQaF flag clear and IRQbF flag generation compete (IRQaF flag setting). ...
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Section 5 Interrupt Controller In this situation, conduct one of the following countermeasures. Countermeasure 1: When clears IRQaF flag, do not use the bit manipulation instruction, read the ISR in bytes. Then write a value in bytes which sets IRQnF ...
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Therefore, if the CPU accidentally executes the instruction, the chip will perform exceptional processing and will enter the break mode. In the break mode, interrupts including the NMI are inhibited and the count of the watch dog timer ...
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Section 5 Interrupt Controller Rev. 7.00 Sep 21, 2005 page 122 of 878 REJ09B0259-0700 ...
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Section 6 Bus Controller 6.1 Overview The H8/3048 Group has an on-chip bus controller that divides the address space into eight areas and can assign different bus specifications to each. This enables different types of memory to be connected easily. ...
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Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. Internal address bus Area decoder Chip select control signals WAIT Internal signals CPU bus request signal DMAC bus request signal Refresh controller bus ...
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Input/Output Pins Table 6.1 summarizes the bus controller’s input/output pins. Table 6.1 Bus Controller Pins Name Abbreviation Chip select Address strobe RD Read HWR High write LWR Low write WAIT Wait ...
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Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the bus controller’s registers. Table 6.2 Bus Controller Registers Address* Name H'FFEC Bus width control register H'FFED Access state control register H'FFEE Wait control register H'FFEF Wait state controller enable ...
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Bits 7 to 0—Areas Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or 16-bit access to the corresponding address areas. Bits ABW7 to ABW0 Description 0 Areas are ...
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Section 6 Bus Controller 6.2.3 Wait Control Register (WCR) WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. Bit 7 — Initial value 1 Read/Write — ...
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Wait State Controller Enable Register (WCER) WCER is an 8-bit readable/writable register that enables or disables wait-state control of external three-state-access areas by the wait-state controller. Bit 7 WCE7 WCE6 Initial value 1 Read/Write R/W WCER is initialized to ...
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Section 6 Bus Controller 6.2.5 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A enables or disables release of the bus to an external device. Bit 7 A23E Initial value ...
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Bit 5—Address 21 Enable (A21E): Enables PA Writing 0 in this bit enables A cannot be modified and PA has its ordinary input/output functions. 6 Bit 5: A21E Description the the PA ...
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Section 6 Bus Controller Bits 7 to 4—Chip Select Enable (CS7E to CS4E): These bits enable or disable output of the corresponding chip select signal. Bit n: CSnE Description 0 Output of chip select signal CS 1 ...
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Operation 6.3.1 Area Division The external address space is divided into areas Each area has a size of 128 kbytes in the 1-Mbyte modes Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general ...
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Section 6 Bus Controller to CS Chip select signals (CS 7 can be selected in ABWCR, ASTCR, WCER, and WCR as shown in table 6.3. Table 6.3 Bus Specifications ABWCR ASTCR WCER ABWn ASTn WCEn 0 0 — ...
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Output Output register (CSCR). A reset leaves pins the corresponding CSCR bits must be set to 1. For details see ...
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Section 6 Bus Controller 6.3.3 Data Bus The H8/3048 Group allows either 8-bit access or 16-bit access to be designated for each of areas 8-bit-access area uses the upper data bus (D upper data bus (D ...
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Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6.4 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper address bus (D pin is always high. Wait states can be inserted. Address bus CS n ...
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Section 6 Bus Controller 8-Bit, Two-State-Access Areas: Figure 6.5 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper address bus (D pin is always high. Wait states cannot be inserted. Address bus CSn AS RD ...
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Three-State-Access Areas: Figures 6.6 to 6.8 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper address bus (D even addresses and the lower address bus (D can be inserted. Address bus ...
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Section 6 Bus Controller Address bus Read access HWR LWR Write access Note ...
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Address bus Read access HWR LWR Write access Note Figure 6.8 ...
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Section 6 Bus Controller 16-Bit, Two-State-Access Areas: Figures 6.9 to 6.11 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper address bus (D even addresses and the lower address bus (D cannot ...
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Address bus CSn AS RD Read access HWR LWR Write access Note Figure 6.10 Bus ...
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Section 6 Bus Controller Address bus CSn AS RD Read access HWR LWR Write access Note Figure 6.11 Bus ...
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Wait Modes Four wait modes can be selected as shown in table 6.5. Table 6.5 Wait Mode Selection ASTCR WCER ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control 0 — — — ...
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Section 6 Bus Controller Wait Mode in Areas Where Wait-State Controller is Disabled External three-state access areas in which the wait-state controller is disabled (ASTn = 1, WCEn = 0) operate in pin wait mode 0. The other wait modes ...
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Wait Modes in Areas Where Wait-State Controller is Enabled External three-state access areas in which the wait-state controller is enabled (ASTn = 1, WCEn = 1) can operate in pin wait mode 1, pin auto-wait mode, or programmable wait mode, ...
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Section 6 Bus Controller Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (T WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system ...
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Programmable Wait Mode: The number of wait states (T inserted in all accesses to external three-state-access areas. Figure 6.15 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). Address bus AS RD Read access ...
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Section 6 Bus Controller Example of Wait State Control Settings: A reset initializes ASTCR and WCER to H'FF and WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can select other wait modes for ...
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Interconnections with Memory (Example) For each area, the bus controller can select two- or three-state access and 16-bit data bus width. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the ...
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Section 6 Bus Controller H8/3048 Group WAIT RD HWR LWR Figure 6.18 Interconnections with Memory (Example) Rev. 7.00 Sep ...
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Bus Arbiter Operation The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are four bus masters: the CPU, DMA controller (DMAC), refresh controller, and an external bus master. When a bus master has ...
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Section 6 Bus Controller DMAC: When the DMAC receives an activation request, it requests the bus right from the bus arbiter. If the DMAC is bus master and the refresh controller or an external bus master requests the bus, the ...
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Figure 6.19 shows the timing when the bus right is requested by an external bus master during a read cycle in a two-state-access area. There is a minimum interval of two states from when the BREQ signal goes low until ...
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Section 6 Bus Controller 6.4 Usage Notes 6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM A different bus control signal timing applies when dynamic RAM or pseudo-static RAM is connected to area 3. For details see section 7, Refresh Controller. ...
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DDR Write Timing: Data written to a data direction register (DDR) to change output to generic input, or vice versa, takes effect starting from the T n cycle. Figure 6.21 shows the timing when the CS Address ...
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Section 6 Bus Controller BREQ Input Timing BREQ BREQ BREQ 6.4.3 After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high level before BACK goes low, the bus arbiter may operate ...
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Section 7 Refresh Controller 7.1 Overview The H8/3048 Group has an on-chip refresh controller that enables direct connection of 16-bit-wide DRAM or pseudo-static RAM (PSRAM). DRAM or pseudo-static RAM can be directly connected to area 3 of the external address ...
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Section 7 Refresh Controller RFSH signal output for refresh control Software-selectable refresh interval Software-selectable self-refresh mode Wait states can be inserted Features as an Interval Timer Refresh timer counter (RTCNT) can be used as an 8-bit up-counter Selection of seven ...
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Input/Output Pins Table 7.1 summarizes the refresh controller’s input/output pins. Table 7.1 Refresh Controller Pins Signal Pin Name RFSH Refresh HWR Upper write/upper column address strobe LWR Lower write/lower column address strobe RD Column address strobe/ write enable CS ...
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Section 7 Refresh Controller 7.2 Register Descriptions 7.2.1 Refresh Control Register (RFSHCR) RFSHCR is an 8-bit readable/writable register that selects the operating mode of the refresh controller. Bit 7 SRFMD PSRAME Initial value 0 Read/Write R/W R/W PSRAM enable and ...
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Bit 7—Self-Refresh Mode (SRFMD): Specifies DRAM or pseudo-static RAM self-refresh during software standby mode. When PSRAME = 1 and DRAME = 0, after the SRFMD bit is set to 1, pseudo-static RAM can be self-refreshed when the H8/3048 Group enters ...
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Section 7 Refresh Controller Bit 3—Address Multiplex Mode Select (M9/M8 The setting of this bit is valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled when the PSRAME or DRAME bit is set ...
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Refresh Timer Control/Status Register (RTMCSR) RTMCSR is an 8-bit readable/writable register that selects the clock source for RTCNT. It also enables or disables interrupt requests when the refresh controller is used as an interval timer. Bit 7 CMF CMIE ...
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Section 7 Refresh Controller Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt requested when the CMF flag is set RTMCSR. The CMIE bit is always cleared to 0 when PSRAME = 1 or ...
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RTCNT is write-disabled when the PSRAME bit or DRAME bit is set to 1. RTCNT is initialized to H' reset and in standby mode. 7.2.4 Refresh Time Constant Register (RTCOR) RTCOR is an 8-bit readable/writable register that determines ...
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Section 7 Refresh Controller 7.3 Operation 7.3.1 Overview One of three functions can be selected for the H8/3048 Group refresh controller: interfacing to DRAM connected to area 3, interfacing to pseudo-static RAM connected to area 3, or interval timing. Table ...
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DRAM Interface: To set up area 3 for connection to 16-bit-wide DRAM, initialize RTCOR, RTMCSR, and RFSHCR in that order, clearing bit PSRAME to 0 and setting bit DRAME to 1. DDR the port 8 data direction ...
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Section 7 Refresh Controller 7.3.2 DRAM Refresh Control Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is determined by the settings of RTCOR and bits CKS2 to CKS0 in RTMCSR. Figure 7.2 illustrates the refresh request interval. ...
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When a refresh request occurs in the refresh request pending state, the refresh controller acquires the bus right, then executes a refresh cycle. If another refresh request occurs during execution of the refresh cycle ignored. Refresh request * ...
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Section 7 Refresh Controller Address Multiplexing: Address multiplexing depends on the setting of the M9/M8 bit in RFSHCR, as described in table 7.5. Figure 7.4 shows the address output timing. Address output is multiplexed only in area 3. Table 7.5 ...
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CAS CAS and 2WE CAS WE WE Modes: The CAS/WE bit in RFSHCR can select two control modes for 16-bit- WE 2CAS wide DRAM: one using UCAS and LCAS; the other using UW and LW. These DRAM pins correspond to ...
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Section 7 Refresh Controller Read cycle Address Row Column bus CS 3 (RAS) HWR (UCAS) HWR (UW) LWR (LW) RFSH AS Note: * 16-bit access Figure 7.5(2) DRAM Control Signal Output Timing (2CAS Refresh Cycle Priority Order: When there are ...