HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 222
HD64F3048VTF8
Manufacturer Part Number
HD64F3048VTF8
Description
IC H8 MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.HD64F3048F16.pdf
(907 pages)
Specifications of HD64F3048VTF8
Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F3048VX8
- Current page: 222 of 907
- Download datasheet (6Mb)
Section 7 Refresh Controller
Rev. 7.00 Sep 21, 2005 page 196 of 878
REJ09B0259-0700
If a bus cycle is prolonged by insertion of wait states, the first refresh request is held, as in the
bus-released state.
If there is contention with a bus request from an external bus master when making a transition
to software standby mode, a one-state bus-released state may occur immediately before the
transition to software standby mode (see figure 7.25).
When using software standby mode, clear the BRLE bit to 0 in BRCR before executing the
SLEEP instruction.
When making a transition to self-refresh mode, the strobe waveform output may not be
guaranteed due to the same kind of contention. This, too, can be prevented by clearing the
BRLE bit to 0 in BRCR.
Figure 7.25 Contention between Bus-Released State and Software Standby Mode
BREQ
BACK
Address bus
Strobe
RFSH
Refresh
request
BACK
Bus-released state
Figure 7.24 Refresh Cycles when Bus is Released
External bus
released state
Refresh cycle
Software standby mode
CPU cycle
Refresh cycle
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