HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 93
HD64F3048VTF8
Manufacturer Part Number
HD64F3048VTF8
Description
IC H8 MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.HD64F3048F16.pdf
(907 pages)
Specifications of HD64F3048VTF8
Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F3048VX8
- Current page: 93 of 907
- Download datasheet (6Mb)
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins
MD
MDS0 are read-only bits. The mode pin (MD
MDCR is read.
3.3
SYSCR is an 8-bit register that controls the operation of the H8/3048 Group.
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 21, Power-Down State.)
When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear
this bit, write 0.
Bit 7: SSBY
0
1
Bit
Initial value
Read/Write
2
to MD
System Control Register (SYSCR)
0
(the current operating mode). MDS2 to MDS0 correspond to MD
SSBY
Software standby
Enables transition to software standby mode
R/W
Description
SLEEP instruction causes transition to sleep mode
SLEEP instruction causes transition to software standby mode
7
0
STS2
R/W
Standby timer select 2 to 0
These bits select the waiting time at
recovery from software standby mode
6
0
STS1
R/W
5
0
2
to MD
STS0
R/W
4
0
User bit enable
Selects whether to use the UI bit in CCR
as a user bit or an interrupt mask bit
0
) levels are latched into these bits when
Rev. 7.00 Sep 21, 2005 page 67 of 878
R/W
UE
3
1
NMI edge select
Selects the valid edge
of the NMI input
Section 3 MCU Operating Modes
NMIEG
R/W
2
0
Reserved bit
2
—
—
REJ09B0259-0700
1
1
to MD
RAM enable
Enables or
disables
on-chip RAM
(Initial value)
0
RAME
. MDS2 to
R/W
0
1
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