HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 468

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

Section 12 Watchdog Timer
12.2.3
RSTCSR is an 8-bit readable and writable * register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Note: * RSTCSR differs from other registers in being more difficult to write. For details see
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire chip
internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to
initialize external system devices.
Rev. 7.00 Sep 21, 2005 page 442 of 878
REJ09B0259-0700
Bit 7: WRST
0
1
Bit
Initial value
Read/Write
Note: * Only 0 can be written in bit 7, to clear the flag.
section 12.2.4, Notes on Register Access.
Reset Control/Status Register (RSTCSR)
Watchdog timer reset
Indicates that a reset signal has been generated
R/(W)
WRST
Description
[Clearing conditions]
Cleared to 0 by reset signal input at RES pin
Cleared by reading WRST when WRST = 1, then writing 0 in WRST
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer
operation
7
0
*
Reset output enable
Enables or disables external output of the reset signal
RSTOE
R/W
6
0
—
—
5
1
—
—
4
1
Reserved bits
—
—
3
1
—
—
2
1
—
—
1
1
(Initial value)
—
—
0
1