HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 234
HD64F3048VTF8
Manufacturer Part Number
HD64F3048VTF8
Description
IC H8 MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.HD64F3048F16.pdf
(907 pages)
Specifications of HD64F3048VTF8
Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F3048VX8
- Current page: 234 of 907
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Section 8 DMA Controller
Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer
activation source. Some of the selectable sources differ between channels A and B.*
Note: * Refer to section 8.3.4, Data Transfer Control Registers (DTCR).
The same internal interrupt can be selected as an activation source for two or more channels at
once. In that case the channels are activated in a priority order, highest-priority channel first. For
the priority order, see section 8.4.9, DMAC Multiple-Channel Operation.
When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a
CPU interrupt.
Rev. 7.00 Sep 21, 2005 page 208 of 878
REJ09B0259-0700
Bit 3: DTIE
0
1
Bit 2: DTS2
0
1
Bit 1: DTS1
0
1
0
1
Description
The DEND interrupt requested by DTE is disabled
The DEND interrupt requested by DTE is enabled
Bit 0: DTS0
0
1
0
1
0
1
0
1
Description
Compare match/input capture A interrupt from ITU
channel 0
Compare match/input capture A interrupt from ITU
channel 1
Compare match/input capture A interrupt from ITU
channel 2
Compare match/input capture A interrupt from ITU
channel 3
Transmit-data-empty interrupt from SCI channel 0
Receive-data-full interrupt from SCI channel 0
Falling edge of DREQ input (channel B)
Transfer in full address mode (channel A)
Low level of DREQ input (channel B)
Transfer in full address mode (channel A)
(Initial value)
(Initial value)
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