HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 621

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

19.3.4
The RAM control register (RAMCR) enables flash-memory updates to be emulated in RAM, and
indicates flash memory errors.
Bit 7—Flash Memory Error (FLER): Indicates that an error occurred while flash memory was
being programmed or erased. When bit 7 is set, flash memory is placed in an error-protect mode. *
Notes: 1. For details, see section 19.5.8, Protect Modes.
Bits 6 to 4—Reserved: Read-only bits, always read as 1.
Bit 3—RAM Select (RAMS)*: Is used with bits 2 to 0 to reassign an area to RAM (see table
19.6). When bit 3 is set, all flash-memory blocks are protected from programming and erasing,
regardless of the values of bits 2 to 0.
Bit
Initial value
Read/Write
Bit 7: FLER
0
1
2. The read data has undetermined values.
RAM Control Register (RAMCR)
FLER
R
7
0
Description
Flash memory is not write/erase-protected (is not in error protect mode *
[Clearing condition]
Reset or hardware standby mode
Indicates that an error occurred while flash memory was being programmed or
erased, and error protection *
[Setting conditions]
Flash memory was read *
or instruction fetch, but not including reading of a RAM area overlapped onto
flash memory).
A hardware exception-handling sequence (other than a reset, trace exception,
invalid instruction, trap instruction, or zero-divide exception) was executed just
before programming or erasing.
The SLEEP instruction (for transition to sleep mode or software standby mode)
was executed during programming or erasing.
A bus was released during programming or erasing.
Section 19 Flash Memory (H8/3048F: Dual Power Supply (V
—
—
6
1
—
—
5
1
2
while being programmed or erased (including vector
1
is in effect
—
—
4
1
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RAMS
R/W
3
0
RAM2
R/W
2
0
REJ09B0259-0700
RAM1
R/W
1
0
(Initial value)
PP
RAM0
= 12 V))
1
R/W
)
0
0
1