UPD70F3747GB-GAH-AX Renesas Electronics America, UPD70F3747GB-GAH-AX Datasheet
UPD70F3747GB-GAH-AX
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UPD70F3747GB-GAH-AX Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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User’s Manual V850ES/HE3, V850ES/HF3, V850ES/HG3, V850ES/HJ3 32-bit Single-Chip Microcontrollers Hardware V850ES/HE3: μ PD70F3747 V850ES/HF3: μ PD70F3750 V850ES/HG3: μ PD70F3752 V850ES/HJ3: μ PD70F3755 μ PD70F3757 Document No. U18854EJ2V0UD00 (2nd edition) Date Published September 2008 N 2008 Printed in Japan ...
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User’s Manual U18854EJ2V0UD ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or a trademark in the United States of America. Windows and Windows NT are ...
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The information in this document is current as of June, 2008. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most ...
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Readers This manual is intended for users who wish to understand the functions of the V850ES/Hx3 and design application systems using the V850ES/Hx3. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/Hx3 ...
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The mark “<R>” shows major revised points. searched by copying an “<R>” in the PDF file and specifying it in the “Find what:” field. The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. ...
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/Hx3 V850ES Architecture User’s Manual V850ES/HE3, V850ES/HF3, V850ES/HG3, V850ES/HJ3 Hardware User’s Manual Documents related to development ...
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CHAPTER 1 INTRODUCTION .................................................................................................................21 1.1 General .....................................................................................................................................21 1.2 Features....................................................................................................................................22 1.2.1 V850ES/HE3 ( 1.2.2 V850ES/HF3 ( 1.2.3 V850ES/HG3 ( 1.2.4 V850ES/HJ3 ( 1.3 Application Fields ...................................................................................................................26 1.4 Ordering Information ..............................................................................................................26 1.5 Pin Configuration (Top View) .................................................................................................27 1.5.1 V850ES/HE3 ( 1.5.2 V850ES/HF3 ...
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V850ES/HE3............................................................................................................................104 4.1.2 V850ES/HF3............................................................................................................................104 4.1.3 V850ES/HG3 ...........................................................................................................................104 4.1.4 V850ES/HJ3 ............................................................................................................................104 4.2 Basic Configuration of Ports............................................................................................... 105 4.2.1 V850ES/HE3............................................................................................................................105 4.2.2 V850ES/HF3............................................................................................................................106 4.2.3 V850ES/HG3 ...........................................................................................................................107 4.2.4 V850ES/HJ3 ............................................................................................................................108 4.3 Port Configuration ................................................................................................................ 109 4.3.1 Port 0 .......................................................................................................................................114 4.3.2 Port 1 .......................................................................................................................................118 4.3.3 ...
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Relationship between programmable wait and external wait ................................................... 251 5.5.4 Programmable address wait function ...................................................................................... 252 5.6 Idle State Insertion Function ................................................................................................253 5.7 Bus Hold Function ................................................................................................................254 5.7.1 Functional outline .................................................................................................................... 254 5.7.2 Bus hold procedure ................................................................................................................. 255 5.7.3 ...
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Functions............................................................................................................................... 396 8.3 Configuration ........................................................................................................................ 397 8.4 Registers ............................................................................................................................... 399 8.5 Operation............................................................................................................................... 416 8.5.1 Interval timer mode (TABnMD2 to TABnMD0 bits = 000) ........................................................417 8.5.2 External event count mode (TABnMD2 to TABnMD0 bits = 001) ............................................426 8.5.3 External trigger ...
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Registers ................................................................................................................................578 12.4 Operation................................................................................................................................581 CHAPTER 13 A/D CONVERTER ..........................................................................................................582 13.1 Overview.................................................................................................................................582 13.2 Functions ...............................................................................................................................582 13.3 Configuration .........................................................................................................................583 13.4 Registers ................................................................................................................................586 13.5 Operation................................................................................................................................594 13.5.1 Basic operation........................................................................................................................ 594 13.5.2 Trigger mode ........................................................................................................................... 595 13.5.3 Operation mode....................................................................................................................... 597 13.5.4 Power-fail compare mode........................................................................................................ ...
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Interrupt Request Signals.................................................................................................... 682 15.6 Operation............................................................................................................................... 683 15.6.1 Single transfer mode (master mode, transmission mode)........................................................683 15.6.2 Single transfer mode (master mode, reception mode) .............................................................685 15.6.3 Single transfer mode (master mode, transmission/reception mode) ........................................687 15.6.4 Single transfer mode (slave mode, ...
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Arbitration ..............................................................................................................................771 16.13 Wakeup Function ..................................................................................................................772 16.14 Communication Reservation ...............................................................................................773 16.14.1 When communication reservation function is enabled (IICF0.IICRSV0 bit = 0) ....................... 773 16.14.2 When communication reservation function is disabled (IICF0.IICRSV0 bit = 1) ...................... 777 16.15 Cautions .................................................................................................................................778 ...
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Debug trap ...............................................................................................................................855 18.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP14) ................................. 857 18.6.1 Noise elimination .....................................................................................................................857 18.6.2 Edge detection.........................................................................................................................857 18.7 Interrupt Acknowledge Time of CPU .................................................................................. 867 18.8 Periods in Which Interrupts Are Not Acknowledged ...
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CHAPTER 22 CLOCK MONITOR .........................................................................................................901 22.1 Functions ...............................................................................................................................901 22.2 Configuration .........................................................................................................................901 22.3 Register ..................................................................................................................................902 22.4 Operation................................................................................................................................903 CHAPTER 23 POWER-ON CLEAR CIRCUIT .....................................................................................906 23.1 Function .................................................................................................................................906 23.2 Configuration .........................................................................................................................906 23.3 Operation................................................................................................................................907 CHAPTER 24 LOW-VOLTAGE DETECTOR........................................................................................908 24.1 Functions ...............................................................................................................................908 24.2 Configuration .........................................................................................................................908 ...
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Connection circuit example......................................................................................................955 28.1.2 Interface signals.......................................................................................................................955 28.1.3 Maskable functions ..................................................................................................................957 28.1.4 Register ...................................................................................................................................957 28.1.5 Operation .................................................................................................................................959 28.1.6 Cautions...................................................................................................................................959 28.2 Debugging Without Using DCU........................................................................................... 960 28.2.1 Circuit connection examples ....................................................................................................960 28.2.2 Maskable functions ..................................................................................................................962 28.2.3 Securement of user resources.................................................................................................962 28.2.4 ...
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Pin leakage current................................................................................................................ 1002 30.6.3 Supply current ....................................................................................................................... 1003 30.7 AC Characteristics ..............................................................................................................1004 30.7.1 CLKOUT output timing .......................................................................................................... 1005 30.8 Basic Operation...................................................................................................................1006 30.9 Flash Memory Programming Characteristics ..................................................................1014 CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/HG3) .....................................................1015 31.1 Absolute Maximum Ratings ...............................................................................................1015 ...
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CHAPTER 33 PACKAGE DRAWINGS .............................................................................................. 1065 <R> CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS......................................................... 1069 APPENDIX A DEVELOPMENT TOOLS............................................................................................. 1070 A.1 Software Package ............................................................................................................... 1072 A.2 Language Processing Software ........................................................................................ 1072 A.3 Control Software................................................................................................................. 1072 A.4 Debugging Tools (Hardware) ............................................................................................ 1073 A.4.1 ...
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The V850ES/Hx3 is one of the products in the NEC Electronics V850 single-chip microcontrollers designed for real- time control applications. 1.1 General The V850ES/Hx3 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions such as ...
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Features μ 1.2.1 V850ES/HE3 ( PD70F3747) Minimum instruction execution time: 31.25 ns (operating with main clock (f 32 bits × 32 registers General-purpose registers: Signed multiplication (16 × 16 → 32 clocks CPU features: Signed multiplication ...
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V850ES/HF3 ( PD70F3750) Minimum instruction execution time: 31.25 ns (operating with main clock (f 32 bits × 32 registers General-purpose registers: Signed multiplication (16 × 16 → 32 clocks CPU features: Signed multiplication (32 × ...
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V850ES/HG3 ( PD70F3752) Minimum instruction execution time: 31.25 ns (operating with main clock (f 32 bits × 32 registers General-purpose registers: Signed multiplication (16 × 16 → 32 clocks CPU features: Signed multiplication (32 × ...
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V850ES/HJ3 ( PD70F3755, 70F3757) Minimum instruction execution time: 31.25 ns (operating with main clock (f 32 bits × 32 registers General-purpose registers: Signed multiplication (16 × 16 → 32 clocks CPU features: Signed multiplication (32 ...
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Application Fields Industrial equipment, air-conditioning-/housing-related equipment, measurement equipment, and consumer electronics 1.4 Ordering Information • V850ES/HE3 Part Number μ 64-pin plastic LQFP (fine pitch) (10 × 10) PD70F3747GB-GAH-AX • V850ES/HF3 Part Number μ 80-pin plastic LQFP (fine pitch) (12 ...
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Pin Configuration (Top View) μ 1.5.1 V850ES/HE3 ( PD70F3747) 64-pin plastic LQFP (fine pitch) (10 × 10) μ PD70F3747GB-GAH-AX AV REF0 AV SS Note 1 FLMD0 V DD Note 2 REGC RESET XT1 XT2 P00/TIAA31/TOAA31 ...
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V850ES/HF3 ( PD70F3750) 80-pin plastic LQFP (fine pitch) (12 × 12) μ PD70F3750GK-GAK- REF0 P00/TIAA31/TOAA31 4 P01/TIAA30/TOAA30 5 P02/NMI/TIAA40/TOAA40 6 P03/INTP0/ADTRG/TIAA41/TOAA41 7 P04/INTP1 8 FLMD0 Note REGC ...
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V850ES/HG3 ( PD70F3752) 100-pin plastic LQFP (fine pitch) (14 × 14) μ PD70F3752GC-UEU-AX 100 REF0 P10/INTP9 4 ...
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V850ES/HJ3 ( PD70F3755, 70F3757) 144-pin plastic LQFP (fine pitch) (20 × 20) μ PD70F3755GJ-GAE-AX μ PD70F3757GJ-GAE- REF0 P10/INTP9 3 P11/INTP10 P00/TIAA31/TOAA31 6 P01/TIAA30/TOAA30 7 FLMD0 Note ...
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Pin identification AD0 to AD15: Address/data bus ADTRG: AD trigger input ANI0 to ANI23: Analog input Address strobe ASTB Analog V REF0 Analog Power supply for bus interface DD BV ...
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Function Block Configuration μ 1.6.1 V850ES/HE3 ( PD70F3747) (1) Internal block diagram NMI INTC INTP0 to INTP7 TIAB00 to TIAB03 16-bit timer/ counter AB TOAB00 to TOAB03 TIAA00 to TIAA40, 16-bit timer/ TIAA01 to TIAA41 counter AA: ...
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Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × ...
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Watchdog timer 2 A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. Either the low-speed internal oscillation clock or the main clock can be selected as the source clock. Watchdog timer 2 generates ...
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V850ES/HF3 ( PD70F3750) (1) Internal block diagram NMI INTC INTP0 to INTP7 TIAB00 to TIAB03 16-bit timer/ counter AB TOAB00 to TOAB03 TIAA00 to TIAA40, 16-bit timer/ TIAA01 to TIAA41 counter AA: TOAA00 to TOAA40, 5 ...
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Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × ...
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Watchdog timer 2 A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. Either the low-speed internal oscillation clock or the main clock can be selected as the source clock. Watchdog timer 2 generates ...
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V850ES/HG3 ( PD70F3752) (1) Internal block diagram NMI INTC INTP0 to INTP10 TIAB00, TIAB10 TIAB01, TIAB11 TIAB02, TIAB12 TIAB03, TIAB13 16-bit timer/ counter AB: TOAB00, TOAB10 2 ch TOAB01, TOAB11 TOAB02, TOAB12 TOAB03, TOAB13 TIAA00 to TIAA40, 16-bit ...
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Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × ...
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Watchdog timer 2 A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. Either the low-speed internal oscillation clock or the main clock can be selected as the source clock. Watchdog timer 2 generates ...
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V850ES/HJ3 ( PD70F3755, 70F3757) (1) Internal block diagram NMI INTC INTP0 to INTP14 TIAB00 to TIAB20 TIAB01 to TIAB21 TIAB02 to TIAB22 TIAB03 to TIAB23 16-bit timer/ counter AB: TOAB00 to TOAB20 3 ch TOAB01 to TOAB21 TOAB02 ...
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Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × ...
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Watch timer This timer counts the reference time period (0.5 s) for counting the subclock (32.768 kHz) or the f (32.768 kHz) from prescaler 3. The watch timer can also be used as an interval timer for the main ...
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Overview of Functions Generic Name V850ES/HE3 μ Product Name PD70F3747 Internal Flash memory 128 KB memory RAM 8 KB External bus interface General-purpose register Clocks Minimum instruction execution time Main clock oscillation Subclock oscillation SSCG PLL multiplication High-speed internal ...
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This section explains the names and functions of the pins of the V850ES/HE3, V850ES/HF3, V850ES/HG3, and V850ES/HJ3. 2.1 Pin Function List Three I/O buffer power supplies, AV and V850ES/HF3). The relationship between the power supplies and the pins is shown ...
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Port pins Pin Name I/O P00 I/O Port 0 7-bit I/O port P01 Input/output can be specified in 1-bit units. P02 On-chip pull-up resistor can be connected in 1-bit P03 units. P04 P05 P06 P10 I/O Port 1 2-bit ...
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Pin Name I/O P60 I/O Port 6 16-bit I/O port P61 Input/output can be specified in 1-bit units. P62 On-chip pull-up resistor can be connected in 1-bit P63 units. P64 P65 P66 P67 P68 P69 P610 P611 P612 P613 P614 ...
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Pin Name I/O P90 I/O Port 9 9-bit I/O port (V850ES/HE3, V850ES/HF3) P91 16-bit I/O port (V850ES/HG3, V850ES/HJ3) P92 Input/output can be specified in 1-bit units. P93 On-chip pull-up resistor can be connected in 1-bit P94 units. P95 P96 P97 ...
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Pin Name I/O PCS0 I/O Port CS 2-bit I/O port (V850ES/HF3, V850ES/HG3) 8-bit I/O port (V850ES/HJ3) PCS1 Input/output can be specified in 1-bit units. PCS2 PCS3 PCS4 PCS5 PCS6 PCS7 PCT0 I/O Port CT 4-bit I/O port (V850ES/HF3, V850ES/HG3) 8-bit ...
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Pin Name I/O PDL10 I/O Port DL 8-bit I/O port (V850ES/HE3) 12-bit I/O port (V850ES/HF3) PDL11 14-bit I/O port (V850ES/HG3) 16-bit I/O port (V850ES/HJ3) PDL12 Input/output can be specified in 1-bit units. PDL13 PDL14 PDL15 Remark HE3: V850ES/HE3, HF3: V850ES/HF3, ...
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Non-port pins Pin Name I/O AD0 I/O Address/data bus for external memory AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 ADTRG Input External trigger input for A/D converter ANI0 Input Analog voltage ...
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Pin Name I/O ANI22 Input Analog voltage input for A/D converter ANI23 ASCKD0 Input Serial clock input (UARTD0) ASTB Output Address strobe signal for external memory − AV Reference voltage for A/D converter REF0 − AV Ground potential for A/D ...
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Pin Name I/O INTP6 Input Maskable interrupt input INTP7 INTP8 INTP9 INTP10 INTP11 INTP12 INTP13 INTP14 KR0 Input Key interrupt input KR1 KR2 KR3 KR4 KR5 KR6 KR7 NMI Input Non-maskable interrupt input PCL Output PCL clock output RD Output ...
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Pin Name I/O SCKB0 I/O Serial clock I/O (CSIB0) SCKB1 Serial clock I/O (CSIB1) SCKB2 Serial clock I/O (CSIB2) 2 SCL00 I/O Serial clock I/O (I C00) SDA00 I/O Serial transmit/receive data I/O (I SIB0 Input Serial receive data input ...
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Pin Name I/O TIAB10 Input Capture trigger input/external event input/external trigger input (TAB1) TIAB11 Capture trigger input (TAB1) TIAB12 TIAB13 TIAB20 Capture trigger input/external event input/external trigger input (TAB2) TIAB21 Capture trigger input (TAB2) TIAB22 TIAB23 TOAA00 Output Timer output ...
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Pin Name I/O TOAB0T1 Output Motor control inverted input TOAB0T2 TOAB0T3 TXDD0 Output Serial transmit data output (UARTD0) TXDD1 Serial transmit data output (UARTD1) TXDD2 Serial transmit data output (UARTD2) Note TXDD3 Serial transmit data output (UARTD3) Note TXDD4 Serial ...
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Pin Status The V850ES/HJ3 has an external bus interface function that enables connection of external memories, such as ROM and RAM, and I/O. Table 2-5 shows the operating status of each external bus interface pin in each operation mode. ...
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Pin I/O Circuit Types and Recommended Connection of Unused Pins Pin Name Alternate Function P00 TIAA31/TOAA31 P01 TIAA30/TOAA30 P02 NMI/TIAA40/TOAA40 P03 INTP0/ADTRG/TIAA41/ TOAA41 P04 INTP1 P05 INTP2/DRST P06 INTP3 P10 INTP9 P11 INTP10 P30 TXDD0 P31 RXDD0/INTP7 P32 ASCKD0/TOAA01/ ...
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Pin Name Alternate Function P60 to P62 NTP11 to INTP13 − P63 to P69 P610 to P613 TIAB20/TOAB20 to TIAB23/TOAB23 − P614 − P615 P70 to P79 ANI0 to ANI9 P710 ANI10 P711 ANI11 P712 to P715 ANI12 to ANI15 ...
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Pin Name Alternate Function P120 to P127 ANI16 to ANI23 − PCD0 to PCD3 PCM0 WAIT − PCM1 CLKOUT PCM2 HLDAK − PCM3 HLDRQ − − PCM4 − PCM5 PCS0 CS0 − PCS1 CS1 − PCS2 CS2 PCS3 CS3 − ...
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Pin Name Alternate Function PDL0 to PDL4 AD0 to AD4 − PDL5 AD5/FLMD1 FLMD1 PDL6 AD6 − PDL7 AD7 − PDL8 to PDL11 AD8 to AD11 − PDL12 AD12 − PDL13 AD13 − PDL14 AD14 PDL15 AD15 − AV REF0 ...
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Pin I/O Circuits Type 2 IN Schmitt-triggered input with hysteresis characteristics Type Data P-ch Output N-ch disable Input enable 62 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit Types (1/2) Type 5-K Data Output disable ...
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Type 5-AF Pull-up enable EV Data Output disable Input enable Pull-down enable Type 11-G AV REF0 Data Output disable AV P-ch Comparator + _ N-ch V REF (threshold voltage Input enable CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin ...
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The CPU of the V850ES/Hx3 is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 Features Minimum instruction execution time: 31.25 ns (at 32 MHz operation) Variable instruction length (16-bit/32-bit length) ...
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CPU Register Set The registers of the V850ES/Hx3 can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual. (1) Program ...
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Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers r31, are available. Any of these registers can be used to store a data variable ...
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System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. ...
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Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to ...
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NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those ...
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Program status word (PSW) The program status word (PSW collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this ...
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Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a ...
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Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the ...
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Operation Modes The V850ES/Hx3 has the following operation modes. • Normal operation mode • Flash memory programming mode • Self-programming mode • On-chip debug mode The normal operation mode or flash memory programming mode is specified according to the ...
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Address Space 3.4.1 CPU address space For instruction addressing combined total external memory area and internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) ...
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Memory map The areas shown below are reserved in the V850ES/Hx3 (64 KB Use prohibited ...
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Note The external memory area is available only in the V850ES/HJ3, and is a use-prohibited area in other products 76 CHAPTER 3 CPU FUNCTION ...
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Areas (1) Internal ROM area reserved as an internal ROM area. (a) Internal ROM (128 KB) 128 KB are allocated to addresses 0000000H to 001FFFFH in the Accessing addresses 0020000H to 00FFFFFH is prohibited. ...
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ROM (512 KB) 512 KB are allocated to addresses 00000000H to 0007FFFFH in the Accessing addresses 00080000H to 000FFFFFH is prohibited. (2) Internal RAM area are reserved as the internal RAM area. (a) Internal RAM ...
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CHAPTER 3 CPU FUNCTION (b) Internal RAM (16 KB are allocated to addresses 03FFB000H to 03FFEFFFH in the following versions. Accessing addresses 03FF0000H to 03FF9FFFH is prohibited. μ • PD70F3750, 70F3752, 70F3755 Figure 3-8. Internal RAM Area (16 ...
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On-chip peripheral I/O area addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Physical address space ...
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Wraparound of data space The result of an operand address calculation operation that exceeds 32 bits is ignored. Therefore, the highest address of the data space, FFFFFFFFH, and the lowest address, 00000000H, are contiguous, and wraparound occurs at the ...
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Data space With the V850ES/Hx3, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25 26-bit address is sign-extended to 32 bits and ...
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Figure 3-12. Recommended Memory Map Program space ...
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Peripheral I/O registers Address Function Register Name FFFFF004H Port DL FFFFF004H Port DLL FFFFF005H Port DLH FFFFF008H Port CS FFFFF00AH Port CT FFFFF00CH Port CM FFFFF00EH Port CD FFFFF024H Port mode register DL FFFFF024H Port mode register DLL FFFFF025H ...
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Address Function Register Name FFFFF0C2H DMA transfer count register 1 FFFFF0C4H DMA transfer count register 2 FFFFF0C6H DMA transfer count register 3 FFFFF0D0H DMA addressing control register 0 FFFFF0D2H DMA addressing control register 1 FFFFF0D4H DMA addressing control register 2 ...
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Address Function Register Name FFFFF128H Interrupt control register FFFFF12AH Interrupt control register FFFFF12CH Interrupt control register FFFFF12EH Interrupt control register FFFFF130H Interrupt control register FFFFF132H Interrupt control register FFFFF134H Interrupt control register FFFFF136H Interrupt control register FFFFF138H Interrupt control register ...
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Address Function Register Name FFFFF184H Interrupt control register FFFFF186H Interrupt control register FFFFF188H Interrupt control register FFFFF18AH Interrupt control register FFFFF18CH Interrupt control register FFFFF18EH Interrupt control register FFFFF190H Interrupt control register FFFFF192H Interrupt control register FFFFF194H Interrupt control register ...
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Address Function Register Name FFFFF214H A/D conversion result register 2 FFFFF215H A/D conversion result register 2H FFFFF216H A/D conversion result register 3 FFFFF217H A/D conversion result register 3H FFFFF218H A/D conversion result register 4 FFFFF219H A/D conversion result register 4H ...
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Address Function Register Name FFFFF23CH A/D conversion result register 22 FFFFF23DH A/D conversion result register 22H FFFFF23EH A/D conversion result register 23 FFFFF23FH A/D conversion result register 23H FFFFF300H Key return mode register FFFFF308H Selector operation control register 0 FFFFF30AH ...
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Address Function Register Name FFFFF42EH Port mode register 7L FFFFF42FH Port mode register 7H FFFFF430H Port mode register 8 FFFFF432H Port mode register 9 FFFFF432H Port mode register 9L FFFFF433H Port mode register 9H FFFFF438H Port mode register 12 FFFFF440H ...
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Address Function Register Name FFFFF541H TAB0 control register 1 FFFFF542H TAB0 I/O control register 0 FFFFF543H TAB0 I/O control register 1 FFFFF544H TAB0 I/O control register 2 FFFFF545H TAB0 option register 0 FFFFF546H TAB0 capture/compare register 0 FFFFF548H TAB0 capture/compare ...
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Address Function Register Name FFFFF5B6H TAA2 capture/compare register 0 FFFFF5B8H TAA2 capture/compare register 1 FFFFF5BAH TAA2 counter read buffer register FFFFF5C0H TAA3 control register 0 FFFFF5C1H TAA3 control register 1 FFFFF5C2H TAA3 I/O control register 0 FFFFF5C3H TAA3 I/O control ...
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Address Function Register Name FFFFF62CH TAB2 capture/compare register 3 FFFFF62EH TAB2 counter read buffer register FFFFF680H Watch timer operation mode register FFFFF690H TMM0 timer control register 0 FFFFF694H TMM0 compare register 0 FFFFF6C0H Oscillation stabilization time selection register FFFFF6C1H PLL ...
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Address Function Register Name FFFFFA03H UARTD0 option control register 0 FFFFFA04H UARTD0 status register FFFFFA05H UARTD0 option control register 1 FFFFFA06H UARTD0 receive data register FFFFFA07H UARTD0 transmit data register FFFFFA10H UARTD1 control register 0 FFFFFA11H UARTD1 control register 1 ...
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Address Function Register Name FFFFFA55H UARTD5 option control register 1 FFFFFA56H UARTD5 receive data register FFFFFA57H UARTD5 transmit data register FFFFFC00H External interrupt falling edge specification register 0 FFFFFC02H External interrupt falling edge specification register 1 FFFFFC06H External interrupt falling ...
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Address Function Register Name FFFFFD06H CSIB0 transmit data register FFFFFD06H CSIB0 transmit data register L FFFFFD10H CSIB1 control register 0 FFFFFD11H CSIB1 control register 1 FFFFFD12H CSIB1 control register 2 FFFFFD13H CSIB1 status register FFFFFD14H CSIB1 receive data register FFFFFD14H ...
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Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850ES/Hx3 has the following ten special registers. • Power save control register (PSC) • Processor clock control register ...
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Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared in ...
Page 101
Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first ...
Page 102
System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After ...
Page 103
Cautions (1) Registers to be set first Be sure to set the following registers first when using the V850ES/Hx3. • System wait control register (VSWC) • On-chip debug mode register (OCDM) • Watchdog timer mode register 2 (WDTM2) After ...
Page 104
Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the CPU bus ...
Page 105
Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before ...
Page 106
Features 4.1.1 V850ES/HE3 O I/O ports Port pins function alternately as other peripheral-function I/O pins O Can be set in input or output mode in 1-bit units. 4.1.2 V850ES/HF3 O I/O ports Port pins function ...
Page 107
Basic Configuration of Ports 4.2.1 V850ES/HE3 The V850ES/HE3 has a total of 51 I/O ports, ports CM, and DL. The port configuration is shown below. Figure 4-1. Port Configuration (V850ES/HE3) Port 0 Port ...
Page 108
V850ES/HF3 The V850ES/HF3 has a total of 67 I/O ports, ports CM, CS, CT, and DL. The port configuration is shown below. Figure 4-2. Port Configuration (V850ES/HF3) Port 0 Port 3 Port 4 ...
Page 109
V850ES/HG3 The V850ES/HG3 has a total of 84 I/O ports, ports CM, CS, CT, and DL. The port configuration is shown below. Figure 4-3. Port Configuration (V850ES/HG3) Port 0 Port 1 Port ...
Page 110
V850ES/HJ3 The V850ES/HJ3 has a total of 128 I/O ports, ports 12, CD, CM, CS, CT, and DL. The port configuration is shown below. Figure 4-4. Port Configuration (V850ES/HJ3) Port 0 Port 1 Port ...
Page 111
Port Configuration (1) Port n register (Pn) Data is input from or output to an external device by writing or reading the Pn register. The Pn register consists of a port latch that holds output data, and a circuit ...
Page 112
Port n mode register (PMn) The PMn register specifies the I/O mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in ...
Page 113
Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port n, ...
Page 114
Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in ...
Page 115
Port setting Set a port as illustrated below. Figure 4-5. Setting of Each Register and Pin Function Port mode Output mode “0” Input mode “1” Alternate function (when two alternate functions are available) Alternate function 1 “0” Alternate function ...
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Port 0 Port 0 I/O settings can be controlled in 1-bit units. Each product has the same number of I/O ports. Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3 Table 4-10. Alternate-Function Pins of Port 0 Function Alternate-Function Name Name Name ...
Page 117
Port register 0 (P0) After reset: 00H (output latch P06 P0n 0 Outputs 0 1 Outputs 1 (2) Port mode register 0 (PM0) After reset: FFH R/W PM0 1 PM06 PM0n 0 Output mode 1 Input mode ...
Page 118
Port mode control register 0 (PMC0) After reset: 00H R/W PMC0 0 PMC06 PMC06 0 I/O port 1 INTP3 input PMC05 0 I/O port 1 INTP2 input PMC04 0 I/O port 1 INTP1 input PMC03 0 I/O port 1 ...
Page 119
Port function control expansion register 0 (PFCE0) After reset: 00H R/W PFCE0 0 0 Remark For the specifications of alternate functions, see 4.3.1 (6) Settings of alternate functions of port 0. (6) Settings of alternate functions of port 0 ...
Page 120
Port 1 Port 1 I/O settings can be controlled in 1-bit units. The number of I/O ports differs for each product. Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3 Table 4-11. Alternate-Function Pins of Port 1 Function Alternate-Function Name Name Name ...
Page 121
Port mode control register 1 (PMC1) After reset: 00H R/W PMC1 0 0 PMC11 0 I/O port 1 INTP10 input PMC10 0 I/O port 1 INTP9 input (4) Pull-up resistor option register 1 (PU1) After reset: 00H R/W PU1 ...
Page 122
Port 3 Port 3 I/O settings can be controlled in 1-bit units. The number of I/O ports differs for each product. Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3 Table 4-12. Alternate-Function Pins of Port 3 Function Alternate-Function Name Name Name ...
Page 123
Port register 3 (P3) (a) V850ES/HE3 After reset: 00H (output latch P3n 0 Outputs 0 1 Outputs 1 (b) V850ES/HF3 After reset: 0000H (output latch (P3H (P3L P3n 0 ...
Page 124
Port mode register 3 (PM3) (a) V850ES/HE3 After reset: FFH R/W PM3 1 PM3n 0 Output mode 1 Input mode (b) V850ES/HF3 After reset: FFFFH 15 PM3 (PM3H) 1 (PM3L) 1 PM3n 0 1 (c) V850ES/HG3, V850ES/HJ3 After reset: ...
Page 125
Port mode control register 3 (PMC3) (a) V850ES/HE3, V850ES/HF3 After reset: 00H R/W PMC3L 0 0 PMC35 0 I/O port 1 TIAA11 input/TOAA11 output PMC34 0 I/O port 1 TIAA10 input/TOAA10 output PMC33 0 I/O port 1 TIAA01 input/TOAA01 ...
Page 126
V850ES/HG3, V850ES/HJ3 (1/2) After reset: 0000H 15 PMC3 (PMC3H) 0 (PMC3L) 0 PMC39 0 1 PMC38 0 1 PMC35 0 1 PMC34 0 1 PMC33 0 1 PMC32 0 1 Note The INTP8 function and RXDD2 function are alternately ...
Page 127
V850ES/HG3, V850ES/HJ3 (2/2) PMC31 0 I/O port 1 RXDD0 input/INTP7 input PMC30 0 I/O port 1 TXDD0 output Note The INTP7 function and RXDD0 function are alternately used. When using as the RXDD0 function, disable edge detection for the ...
Page 128
Settings of alternate functions of port 3 PFC35 0 TIAA11 input 1 TOAA11 output PFC34 0 TIAA10 input 1 TOAA10 output PFC33 0 TIAA01 input 1 TOAA01 output PFCE32 PFC32 126 ...
Page 129
Pull-up resistor option register 3 (PU3) (a) V850ES/HE3 After reset: 00H R/W PU3L 0 0 PU3n 0 Do not connect 1 Connect (b) V850ES/HF3 After reset: 0000H 15 PU3 (PU3H) 0 (PU3L) 0 PU3n 0 Do not connect 1 ...
Page 130
Port 4 Port 4 I/O settings can be controlled in 1-bit units. Each product has the same number of I/O ports, but the alternate functions of the pins differ. Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3 Table 4-13. Alternate-Function Pins ...
Page 131
Port mode register 4 (PM4) After reset: FFH R/W PM4 1 1 PM4n 0 Output mode 1 Input mode (3) Port mode control register 4 (PMC4) After reset: 00H R/W PMC4 0 PMC42 0 I/O port 1 SCKB0 I/O/KR2 ...
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Port function control expansion register 4 (PFCE4) ( After reset: 00H R/W PFCE4 0 Remark For the specifications of alternate functions, see 4.3.4 (6) Settings of alternate functions of port 4. (6) Settings of alternate functions of port 4 ...
Page 133
Port 5 Port 5 I/O settings can be controlled in 1-bit units. The number of I/O ports differs for each product. Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3 Table 4-14. Alternate-Function Pins of Port 5 Function Alternate-Function Name Name Name ...
Page 134
Port mode register 5 (PM5) After reset: FFH R/W PM5 1 PM5n 0 Output mode 1 Input mode (3) Port mode control register 5 (PMC5) After reset: 00H R/W PMC5 0 PMC55 0 I/O port 1 KR5 input/TOAB0B3 output ...
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Port function control register 5 (PFC5) After reset: 00H R/W PFC5 0 0 Remark For the specifications of alternate functions, see 4.3.5 (6) Settings of alternate functions of port 5. (5) Port function control expansion register 5 (PFCE5) After ...
Page 136
PFCE52 PFC52 PFCE51 PFC51 PFCE50 PFC50 (7) Pull-up resistor option register 5 (PU5) After reset: 00H ...
Page 137
Port 6 (V850ES/HJ3 only) Port 6 I/O settings can be controlled in 1-bit units. The number of I/O ports differs for each product. Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3 Table 4-15. Alternate-Function Pins of Port 6 Function Alternate-Function Name ...
Page 138
Port register 6 (P6) (V850ES/HJ3 only) After reset: 0000H (output latch (P6H) P615 (P6L) P67 P6n 0 Outputs 0 1 Outputs 1 Remarks 1. The P6 register can be read or written in 16-bit units. However, when ...
Page 139
Port mode control register 6 (PMC6) (V850ES/HJ3 only) After reset: 0000H 15 PMC6 (PMC6H) 0 (PMC6L) 0 PMC613 0 I/O port 1 TIAB23 input/TOAB23 output PMC612 0 I/O port 1 TIAB22 input/TOAB22 output PMC611 0 I/O port 1 TIAB21 ...
Page 140
Port function control register 6 (PFC6) (V850ES/HJ3 only) After reset: 0000H 15 PFC6 (PFC6H) 0 (PFC6L) 0 PFC613 0 1 PFC612 0 1 PFC611 0 1 PFC610 0 1 PFC62 0 1 PFC61 0 1 PFC60 0 1 Remarks ...
Page 141
Pull-up resistor option register 6 (PU6) (V850ES/HJ3 only) After reset: 0000H 15 PU6 (PU6H) PU615 PU614 (PU6L) PU67 PU66 PU6n 0 Do not connect 1 Connect Remarks 1. The PU6 register can be read or written in 16-bit units. ...
Page 142
Port 7 Port 7 I/O settings can be controlled in 1-bit units. The number of I/O ports differs for each product. Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3 Table 4-16. Alternate-Function Pins of Port 7 Function Alternate-Function Name Name Name ...
Page 143
Port register 7H, port register 7L (P7H, P7L) (a) V850ES/HE3 After reset: 00H (output latch P7H 0 0 P7L P77 P76 P7n 0 Outputs 0 1 Outputs 1 (b) V850ES/HF3 After reset: 00H (output latch ...
Page 144
Port mode register 7H, port mode register 7L (PM7H, PM7L) (a) V850ES/HE3 After reset: FFH R/W 7 PM7H 1 PM7L PM77 PM76 PM7n 0 Output mode 1 Input mode (b) V850ES/HF3 After reset: FFH R/W 7 PM7H 1 PM7L ...
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Port mode control register 7H, port mode control register 7L (PMC7H, PMC7L) (a) V850ES/HE3 After reset: 00H R PMC7H 0 0 PMC7L PMC77 PMC76 PMC7n 0 I/O port 1 ANIn input (b) V850ES/HF3 After reset: 00H R/W ...
Page 146
Port 8 (V850ES/HJ3 only) Port 8 I/O settings can be controlled in 1-bit units. The number of I/O ports differs for each product. Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3 μ Note In the PD70F3755, the alternate functions of the ...
Page 147
Port mode register 8 (PM8) (V850ES/HJ3 only) After reset: FFH R/W PM8 1 1 PM8n 0 Output mode 1 Input mode (3) Port mode control register 8 (PMC8) (V850ES/HJ3 only) After reset: 00H R/W PMC8 0 0 PMC81 0 ...
Page 148
Port 9 Port 9 which I/O settings can be controlled in 1-bit units. The number of I/O ports differs for each product. Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3 Table 4-18. Alternate-Function Pins of Port 9 Function Alternate-Function Name Name ...
Page 149
Port register 9 (P9) (a) V850ES/HE3, V850ES/HF3 After reset: 0000H (output latch (P9H) P915 P914 (P9L) P97 P96 P9n 0 Outputs 0 1 Outputs 1 (b) V850ES/HG3, V850ES/HJ3 After reset: 0000H (output latch ...
Page 150
Port mode register 9 (PM9) (a) V850ES/HE3, V850ES/HF3 After reset: FFFFH 15 PM9 (PM9H) PM915 (PM9L) PM97 PM9n 0 1 (b) V850ES/HG3, V850ES/HJ3 After reset: FFFFH 15 PM9 (PM9H) PM915 (PM9L) PM97 PM9n 0 1 Remarks 1. The PM9 ...
Page 151
Port mode control register 9 (PMC9) (a) V850ES/HE3, V850ES/HF3 After reset: 0000H 15 PMC9 (PMC9H) PMC915 PMC914 PMC913 (PMC9L) PMC97 PMC915 0 I/O port 1 INTP6 input/SCL00 I/O PMC914 0 I/O port 1 INTP5 input/SDA00 I/O PMC913 0 I/O ...
Page 152
V850ES/HG3 After reset: 0000H 15 PMC9 (PMC9H) PMC915 PMC914 PMC913 (PMC9L) PMC97 PMC915 0 1 PMC914 0 1 PMC913 0 1 PMC99 0 1 PMC98 0 1 PMC97 0 1 PMC96 0 1 PMC95 0 1 150 CHAPTER 4 ...
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CHAPTER 4 PORT FUNCTIONS PMC94 Specification of P94 pin operation mode 0 I/O port 1 TIAB13 input/TOAB13 output PMC93 Specification of P93 pin operation mode 0 I/O port 1 TIAB12 input/TOAB12 output PMC92 Specification of P92 pin operation mode 0 ...
Page 154
V850ES/HJ3 (1/2) After reset: 0000H 15 PMC9 (PMC9H) PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 (PMC9L) PMC97 PMC915 0 1 PMC914 0 1 PMC913 0 1 PMC912 0 1 PMC911 0 1 PMC910 0 1 PMC99 0 1 μ Note ...
Page 155
V850ES/HJ3 (2/2) PMC98 0 I/O port 1 SOB1 output/TIAB03 input/TOAB03 output PMC97 0 I/O port 1 SIB1 input/TIAA20 input/TOAA20 output PMC96 0 I/O port 1 TIAA21 input/TOAA21 output PMC95 0 I/O port 1 TIAB10 input/TOAB10 output PMC94 0 I/O ...
Page 156
Port function control register 9 (PFC9) (a) V850ES/HE3, V850ES/HF3 After reset: 0000H 15 PFC9 (PFC9H) PFC915 PFC914 (PFC9L) PFC97 (b) V850ES/HG3 After reset: 0000H 15 PFC9 (PFC9H) PFC915 PFC914 (PFC9L) PFC97 (c) V850ES/HJ3 After reset: 0000H 15 PFC9 (PFC9H) ...
Page 157
Port function control expansion register 9 (PFCE9) (a) V850ES/HE3, V850ES/HF3 After reset: 0000H 15 PFCE9 (PFCE9H) PFCE915 PFCE914 PFCE913 (PFCE9L) PFCE97 PFCE96 (b) V850ES/HG3 After reset: 0000H 15 PFCE9 (PFCE9H) PFCE915 PFCE914 PFCE913 (PFCE9L) PFCE97 PFCE96 (c) V850ES/HJ3 After ...
Page 158
Settings of alternate functions of port 9 (a) V850ES/HE3, V850ES/HF3 PFCE915 PFC915 PFCE914 PFC914 PFCE913 PFC913 ...
Page 159
PFCE96 PFC96 PFCE91 PFC91 PFCE90 PFC90 Note The KR7 function and RXDD1 function are alternately used. ...
Page 160
V850ES/HG3 PFCE915 PFC915 PFCE914 PFC914 PFCE913 PFC913 PFCE99 PFC99 ...
Page 161
PFCE95 PFC95 PFCE94 PFC94 PFCE93 PFC93 PFCE92 PFC92 ...
Page 162
V850ES/HJ3 PFCE915 PFC915 PFCE914 PFC914 PFCE913 PFC913 Note 1 PFCE912 PFC912 ...
Page 163
CHAPTER 4 PORT FUNCTIONS PFCE99 PFC99 0 0 Setting prohibited 0 1 SCKB1 I TIAB00 input 1 1 TOAB00 output PFCE98 PFC98 0 0 Setting prohibited 0 1 SOB1 output 1 0 TIAB03 input 1 1 TOAB03 output ...
Page 164
PFCE92 PFC92 PFCE91 PFC91 PFCE90 PFC90 Note The KR7 function and RXDD1 function are alternately used. ...
Page 165
Pull-up resistor option register 9 (PU9) (a) V850ES/HE3, V850ES/HF3 After reset: 0000H 15 PU9 (PU9H) PU915 PU914 (PU9L) PU97 PU96 PU9n Control of on-chip pull-up resistor connection ( 15 ...
Page 166
Port 9 function register H (PF9H) After reset: 00H R/W PF9H PF915 PF914 PF9n 0 Normal output 1 N-ch open-drain output Caution When using P915 and P914 as N-ch open-drain-output alternate-function pins, set in the following sequence. Be sure ...
Page 167
Port 12 (V850ES/HJ3 only) Port 12 I/O settings can be controlled in 1-bit units. The number of I/O ports differs for each product. Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3 Table 4-19. Alternate-Function Pins of Port 12 Function Alternate-Function Name ...
Page 168
Port mode register 12 (PM12) (V850ES/HJ3 only) After reset: FFH R/W PM12 PM127 PM126 PM12n 0 Output mode 1 Input mode (3) Port mode control register 12 (PMC12) (V850ES/HJ3 only) After reset: 00H R/W PMC12 PMC127 PMC126 PMC125 PMC124 ...
Page 169
Port CD (V850ES/HJ3 only) Port CD I/O settings can be controlled in 1-bit units. The number of I/O ports differs for each product. Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3 Table 4-20. Alternate-Function Pins of Port CD Function Alternate-Function Name ...
Page 170
Port CM Port CM I/O settings can be controlled in 1-bit units. The number of I/O ports differs for each product. Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3 Table 4-21. Alternate-Function Pins of Port CM Function Alternate-Function Name Name Name ...
Page 171
Port register CM (PCM) (a) V850ES/HE3 After reset: 00H (output latch) PCM 0 0 PCMn 0 Outputs 0 1 Outputs 1 (b) V850ES/HF3, V850ES/HG3 After reset: 00H (output latch) PCM 0 0 PCMn 0 Outputs 0 1 Outputs 1 ...
Page 172
Port mode register CM (PMCM) (a) V850ES/HE3 After reset: FFH R/W PMCM 1 PMCMn 0 Output mode 1 Input mode (b) V850ES/HF3, V850ES/HG3 After reset: FFH R/W PMCM 1 PMCMn 0 Output mode 1 Input mode (c) V850ES/HJ3 After ...
Page 173
Port mode control register CM (PMCCM) (a) V850ES/HE3, V850ES/HF3, V850ES/HG3 After reset: 00H R/W PMCCM 0 0 PMCCM1 0 I/O port 1 CLKOUT output (b) V850ES/HJ3 After reset: 00H R/W PMCCM 0 0 PMCCM3 0 I/O port 1 HLDRQ ...
Page 174
Port CS Port CSI/O settings can be controlled in 1-bit units. The number of I/O ports differs for each product. Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3 Table 4-22. Alternate-Function Pins of Port CS Function Alternate-Function Name Name Name PCS0 ...
Page 175
Port register CS (PCS) (a) V850ES/HF3, V850ES/HG3 After reset: 00H (output latch) PCS 0 0 PCSn 0 Outputs 0 1 Outputs 1 (b) V850ES/HJ3 After reset: 00H (output latch) PCS PCS7 PCS6 PCSn 0 Outputs 0 1 Outputs 1 ...
Page 176
Port mode register CS (PMCS) (a) V850ES/HF3, V850ES/HG3 After reset: FFH R/W PMCS 0 PMCSn 0 Output mode 1 Input mode (b) V850ES/HJ3 After reset: FFH R/W PMCS PMCS7 PMCS6 PMCSn 0 Output mode 1 Input mode 174 CHAPTER ...
Page 177
Port mode control register CS (PMCCS) (V850ES/HJ3 only) After reset: 00H R/W PMCCS 0 0 PMCCS3 0 I/O port 1 CS3 output PMCCS2 0 I/O port 1 CS2 output PMCCS1 0 I/O port 1 CS1 output PMCCS0 0 I/O ...
Page 178
Port CT Port CT I/O settings can be controlled in 1-bit units. The number of I/O ports differs for each product. Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3 Table 4-23. Alternate-Function Pins of Port CT Function Alternate-Function Name Name Name ...
Page 179
Port register CT (PCT) (a) V850ES/HF3, V850ES/HG3 After reset: 00H (output latch) PCT 0 PCT6 PCTn 0 Outputs 0 1 Outputs 1 (b) V850ES/HJ3 After reset: 00H (output latch) PCT PCT7 PCT6 PCTn 0 Outputs 0 1 Outputs 1 ...
Page 180
Port mode register CT (PMCT) (a) V850ES/HF3, V850ES/HG3 After reset: FFH R/W PMCT 1 PMCT6 PMCTn 0 Output mode 1 Input mode (b) V850ES/HJ3 After reset: FFH R/W PMCT PMCT7 PMCT6 PMCTn 0 Output mode 1 Input mode 178 ...
Page 181
Port mode control register CT (PMCCT) (V850ES/HJ3 only) After reset: 00H R/W PMCCT 0 PMCCT6 PMCCT6 0 I/O port 1 ASTB output PMCCT4 0 I/O port 1 RD output PMCCT1 0 I/O port 1 WR1 output PMCCT0 0 I/O ...
Page 182
Port DL Port DL I/O settings can be controlled in 1-bit units. The number of I/O ports differs for each product. Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3 Table 4-24. Alternate-Function Pins of Port DL Function Alternate-Function Name Name Name ...
Page 183
Port register DL (PDL) (a) V850ES/HE3 After reset: 00H (output latch) PDLL PDL7 PDL6 PDLn 0 Outputs 0 1 Outputs 1 (b) V850ES/HF3 After reset: 0000H (output latch) 15 PDL (PDLH) 0 (PDLL) PDL7 PDL6 PDLn 0 Outputs 0 ...
Page 184
V850ES/HJ3 After reset: 0000H (output latch) 15 PDL (PDLH) PDL15 (PDLL) PDL7 PDLn 0 1 Remarks 1. The PDL register can be read or written in 16-bit units. However, when using the higher 8 bits of the PDL register ...
Page 185
V850ES/HF3 After reset: FFFFH 15 PMDL (PMDLH) 1 (PMDLL) PMDL7 PMDLn 0 Output mode 1 Input mode (c) V850ES/HG3 After reset: FFFFH 15 PMDL (PMDLH) 1 (PMDLL) PMDL7 PMDLn 0 Output mode 1 Input mode (d) V850ES/HJ3 After reset: ...
Page 186
Port mode control register DL (PMCDL) (V850ES/HJ3 only) After reset: FFFFH 15 PMCDL (PMCDLH) PMCDL15 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn 0 1 Remarks 1. The PMCDL register can be read or written in 16-bit ...
Page 187
Block Diagrams of Port WR PM PMmn WR PORT Pmn PUmn WR PM PMmn WR PORT Pmn Address RD CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of Type C Output buffer control Address Input buffer ...
Page 188
WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used WR PORT Pmn Address RD 186 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of Type D0 Output buffer control Output data selection Input buffer control ...
Page 189
CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of Type D0 PUmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used WR PORT Pmn Address RD User’s Manual U18854EJ2V0UD EV DD Pull-up control ...
Page 190
WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 when alternate function is used 188 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of Type D1 Output buffer control Input buffer control Input control of ...
Page 191
CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of Type D1 PUmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 in alternate-function mode User’s Manual U18854EJ2V0UD EV Pull-up control Output buffer control ...
Page 192
Figure 4-12. Block Diagram of Type D1- PUmn WR INTR INTRmn WR INTF INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 in alternate-function mode 190 CHAPTER 4 PORT FUNCTIONS Pull-up control ...
Page 193
CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of Type D1A WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD User’s Manual U18854EJ2V0UD Output buffer control Input buffer control P-ch Input signal 1 when alternate function is used ...
Page 194
Figure 4-14. Block Diagram of Type D1O1- PUmn WR INTR INTRmn WR INTF INTFmn WR OCDM OCDM0 WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 when Edge alternate function is used detection ...
Page 195
CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of Type D2 WR PMC Output enable signal 1 when alternate function is used PMCmn WR PM PMmn Output signal 1 when alternate function is used WR PORT Pmn Address Input enable ...
Page 196
Figure 4-16. Block Diagram of Type D3- PUmn WR INTR INTRmn WR INTF INTFmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1-1 when alternate function is used (INTPx) Input signal 1-2 when ...
Page 197
CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of Type E01 PUmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 when alternate function is used WR PORT Pmn Address RD Input signal 2 when ...
Page 198
Figure 4-18. Block Diagram of Type E10 PUmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 2 in alternate-function mode WR PORT Pmn Address RD Input signal 1 in alternate-function mode 196 CHAPTER 4 PORT ...
Page 199
CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of Type E11 PUmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Pmn Address RD Input signal 1 when alternate function is used Input signal 2 when ...
Page 200
Figure 4-20. Block Diagram of Type E21 PUmn Output enable signal 1 in alternate-function mode WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal 1 in alternate-function mode WR PORT Pmn Address RD Input signal 1 ...