UPD70F3747GB-GAH-AX Renesas Electronics America, UPD70F3747GB-GAH-AX Datasheet - Page 13

• Manufacturer Part Number: UPD70F3747GB-GAH-AX
• Description: MCU 32BIT V850ES/HX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Hx3r

Specifications of UPD70F3747GB-GAH-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 6 CLOCK GENERATION FUNCTION ...............................................................................260
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) ..............................................................288
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB) ..............................................................396
5.6
5.7
5.8
5.9
6.1
6.2
6.3
6.4
6.5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8.1
5.5.3
5.5.4
Idle State Insertion Function ................................................................................................253
Bus Hold Function ................................................................................................................254
5.7.1
5.7.2
5.7.3
Bus Priority ............................................................................................................................256
Bus Timing .............................................................................................................................257
Overview.................................................................................................................................260
Configuration .........................................................................................................................261
Registers ................................................................................................................................264
Operation................................................................................................................................273
6.4.1
6.4.2
6.4.3
PLL/SSCG Function ..............................................................................................................276
6.5.1
6.5.2
6.5.3
6.5.4
Overview.................................................................................................................................288
Functions ...............................................................................................................................288
Configuration .........................................................................................................................289
Registers ................................................................................................................................291
Operation................................................................................................................................305
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
Timer-Tuned Operation Function ........................................................................................375
7.6.1
7.6.2
7.6.3
Cascade Connection.............................................................................................................388
Selector Function ..................................................................................................................393
Cautions .................................................................................................................................395
Overview.................................................................................................................................396
Relationship between programmable wait and external wait ................................................... 251
Programmable address wait function ...................................................................................... 252
Functional outline .................................................................................................................... 254
Bus hold procedure ................................................................................................................. 255
Operation in power save mode................................................................................................ 255
Setting CPU clock.................................................................................................................... 273
Operation of each clock........................................................................................................... 274
Clock output function ............................................................................................................... 275
Overview ................................................................................................................................. 276
Registers ................................................................................................................................. 276
Using PLL ................................................................................................................................ 283
Using SSCG ............................................................................................................................ 285
Interval timer mode (TAAnMD2 to TAAnMD0 bits = 000) ........................................................ 306
External event count mode (TAAnMD2 to TAAnMD0 bits = 001) ............................................ 315
External trigger pulse output mode (TAAnMD2 to TAAnMD0 bits = 010) ................................ 323
One-shot pulse output mode (TAAnMD2 to TAAnMD0 bits = 011).......................................... 335
PWM output mode (TAAnMD2 to TAAnMD0 bits = 100) ......................................................... 342
Free-running timer mode (TAAnMD2 to TAAnMD0 bits = 101) ............................................... 351
Pulse width measurement mode (TAAnMD2 to TAAnMD0 bits = 110).................................... 368
Timer output operations........................................................................................................... 374
Free-running timer mode (during timer-tuned operation) ......................................................... 377
PWM output mode (during timer-tuned operation)................................................................... 384
Triangular PWM output mode (during timer-tuned operation) (V850ES/HJ3 only) .................. 386
User’s Manual U18854EJ2V0UD
11