UPD70F3747GB-GAH-AX Renesas Electronics America, UPD70F3747GB-GAH-AX Datasheet - Page 12

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UPD70F3747GB-GAH-AX

Manufacturer Part Number
UPD70F3747GB-GAH-AX
Description
MCU 32BIT V850ES/HX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Hx3r
Datasheet

Specifications of UPD70F3747GB-GAH-AX

Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
51
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3747GB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
CHAPTER 5 BUS CONTROL FUNCTION (V850ES/HJ3 ONLY) .................................................... 238
10
4.2
4.3
4.4
4.5
4.6
5.1
5.2
5.3
5.4
5.5
4.1.1
4.1.2
4.1.3
4.1.4
Basic Configuration of Ports............................................................................................... 105
4.2.1
4.2.2
4.2.3
4.2.4
Port Configuration ................................................................................................................ 109
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.12
4.3.13
4.3.14
4.3.15
Block Diagrams of Port........................................................................................................ 185
Port Register Settings When Alternate Function Is Used ................................................ 223
Cautions ................................................................................................................................ 233
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
Features................................................................................................................................. 238
Bus Control Pins................................................................................................................... 239
5.2.1
5.2.2
Memory Block Function....................................................................................................... 240
Bus Access ........................................................................................................................... 241
5.4.1
5.4.2
5.4.3
Wait Function ........................................................................................................................ 250
5.5.1
5.5.2
V850ES/HE3............................................................................................................................104
V850ES/HF3............................................................................................................................104
V850ES/HG3 ...........................................................................................................................104
V850ES/HJ3 ............................................................................................................................104
V850ES/HE3............................................................................................................................105
V850ES/HF3............................................................................................................................106
V850ES/HG3 ...........................................................................................................................107
V850ES/HJ3 ............................................................................................................................108
Port 0 .......................................................................................................................................114
Port 1 .......................................................................................................................................118
Port 3 .......................................................................................................................................120
Port 4 .......................................................................................................................................128
Port 5 .......................................................................................................................................131
Port 6 (V850ES/HJ3 only)........................................................................................................135
Port 7 .......................................................................................................................................140
Port 8 (V850ES/HJ3 only)........................................................................................................144
Port 9 .......................................................................................................................................146
Port 12 (V850ES/HJ3 only)......................................................................................................165
Port CD (V850ES/HJ3 only).....................................................................................................167
Port CM ...................................................................................................................................168
Port CS ....................................................................................................................................172
Port CT ....................................................................................................................................176
Port DL ....................................................................................................................................180
Cautions on setting port pins ...................................................................................................233
Cautions on bit manipulation instruction for port n register (Pn)...............................................236
Cautions on on-chip debug pins...............................................................................................237
Cautions on P05/INTP2/DRST# pin.........................................................................................237
Cautions on P53 pin when power is turned on.........................................................................237
Hysteresis characteristics ........................................................................................................237
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed...............239
Pin status in each operation mode...........................................................................................239
Number of clocks for access....................................................................................................241
Bus size setting function ..........................................................................................................242
Access by bus size ..................................................................................................................243
Programmable wait function ....................................................................................................250
External wait function...............................................................................................................251
User’s Manual U18854EJ2V0UD

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