UPD70F3747GB-GAH-AX Renesas Electronics America, UPD70F3747GB-GAH-AX Datasheet - Page 888

• Manufacturer Part Number: UPD70F3747GB-GAH-AX
• Description: MCU 32BIT V850ES/HX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Hx3r

Specifications of UPD70F3747GB-GAH-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

886
Non-maskable interrupt request
signal
Maskable interrupt request signal
Item
Main clock oscillator
Subclock oscillator
Low-speed internal oscillator (f
High-speed internal oscillator (f
PLL
SSCG
CPU
Port function
External bus interface
Timer AA (TAA0 to TAA4)
Timer AB (TAB0 to TAB2)
Timer M (TMM0)
Watch timer
Watchdog timer 2
A/D converter
Serial interface
DMA
Interrupt controller
Key interrupt function (KR)
Clock monitor
Power-on clear circuit
Low-voltage detector
Regulator
Internal data
(2) Releasing STOP mode by reset
Remark
The same operation as the normal reset operation is performed.
Release Source
Table 20-10 shows the maximum specifications of the V850ES/HJ3. Some of the functions shown in this
table are not supported by the V850ES/HE3, V850ES/HF3, and V850ES/HG3. For details, see Table 1-
1 V850ES/Hx3 Function List.
Setting of STOP Mode
Table 20-9. Operation After Releasing STOP Mode by Interrupt Request Signal
UARTD0 to UARTD5
CSIB0 to CSIB2
I
2
C00
RL
RH
)
)
Execution branches to the handler address after securing the oscillation stabilization time.
Execution branches to the handler address
or the next instruction is executed after
securing the oscillation stabilization time.
Table 20-10. Operating Status in STOP Mode
Stops oscillation
Oscillation enabled
Stops oscillation
Stops operation
Stops operation
Stops operation
Retains status before STOP mode was set
See 2.2 Pin States.
Stops operation
Stops operation
Operable when f
count clock
Stops operation
Operable when f
Stops operation
Stops operation (but UARTD0 is operable when the ASCKD0 input clock is selected)
Operable when the SCKBn input clock is selected as the count clock
Stops operation
Stops operation
Stops operation (but STOP mode release is possible)
Operable
Stops operation
Operable
Operable
Continues operation
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the STOP mode was set.
CHAPTER 20 STANDBY FUNCTION
Interrupt Enabled (EI) Status
When Subclock Is Not Used
User’s Manual U18854EJ2V0UD
RL
RL
/8 is selected as the
is selected as the count clock
−
Operating Status
The next instruction is executed after
securing the oscillation stabilization time.
Oscillates
Operable when INTWT, f
selected as the count clock
Operable when f
count clock
Interrupt Disabled (DI) Status
When Subclock Is Used
XT
is selected as the
RL
/8, or f
XT
is