UPD70F3747GB-GAH-AX Renesas Electronics America, UPD70F3747GB-GAH-AX Datasheet - Page 27

• Manufacturer Part Number: UPD70F3747GB-GAH-AX
• Description: MCU 32BIT V850ES/HX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Hx3r

Specifications of UPD70F3747GB-GAH-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1.2.4
Minimum instruction execution time: 31.25 ns (operating with main clock (f
General-purpose registers:
CPU features:
Memory space:
Interrupts and exceptions:
I/O lines:
Timer function:
Serial interface:
A/D converter:
DMA controller:
DCU (debug control unit):
Clock generator:
Low-speed internal oscillation clock (f
High-speed internal oscillation clock (f
Power-save functions:
Package:
V850ES/HJ3 (
• Internal memory:
• External bus interface:
μ
PD70F3755, 70F3757)
32 bits × 32 registers
Signed multiplication (16 × 16 → 32): 1 to 2 clocks
Signed multiplication (32 × 32 → 64): 1 to 5 clocks
Saturated operations (overflow and underflow detection functions included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
64 MB of linear address space (for programs and data)
External expansion: Up to 256 KB
Non-maskable interrupts: 2 sources (external: 1, internal: 1)
Maskable interrupts:
Software exceptions:
Exception trap:
I/O ports:
16-bit interval timer M (TMM):
16-bit timer/event counter AA (TAA):
16-bit timer/event counter AB (TAB):
Watch timer:
Watchdog timer 2:
Asynchronous serial interface D (UARTD):
3-wire variable-length serial interface B (CSIB): 3 channels
I
10-bit resolution: 24 channels
4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory)
JTAG interface
During main clock or subclock operation
7-level CPU clock (f
Clock-through mode/PLL mode (×8)/SSCG mode selectable
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
144-pin plastic LQFP (fine pitch) (20 × 20)
2
C bus:
RAM:
Flash memory: 256 KB (
Multiplexed bus
8-/16-bit data bus sizing function
Wait function
Idle state function
Bus hold function
• Programmable wait function
• External wait function
RL
RH
CHAPTER 1 INTRODUCTION
): 240 kHz (TYP.)
User’s Manual U18854EJ2V0UD
): 8 MHz (TYP.)
128
XX
16 KB (
, f
XX
/2, f
72 sources (external: 15, internal: 57) (
78 sources (external: 15, internal: 63) (
32 sources
2 sources
μ
XX
PD70F3755)/32 KB (
μ
PD70F3755)/512 KB (
/4, f
XX
/8, f
1 channel
5 channels
3 channels
1 channel
1 channel
XX
/16, f
XX
) of 32 MHz)
XX
3 channels (
6 channels (
1 channel
/32, f
μ
PD70F3757)
μ
PD70F3757)
XT
)
μ
μ
PD70F3755)
PD70F3757)
μ
μ
PD70F3755)
PD70F3757)
25