UPD70F3747GB-GAH-AX Renesas Electronics America, UPD70F3747GB-GAH-AX Datasheet - Page 535

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UPD70F3747GB-GAH-AX

Manufacturer Part Number
UPD70F3747GB-GAH-AX
Description
MCU 32BIT V850ES/HX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Hx3r
Datasheet

Specifications of UPD70F3747GB-GAH-AX

Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
51
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3747GB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
10.4.3 Interrupt culling function
• The interrupts to be culled are INTTAB0CC0 (crest interrupt) and INTTAB0OV (valley interrupt).
• The TAB0OPT1.TAB0ICE bit is used to enable output of the INTTAB0CC0 interrupt and the number of times the
• The TAB0OPT1.TAB0IOE bit is used to enable output of the INTTAB0OV interrupt and the number of times the
• The TAB0RDE bit of TAB0OPT2 is used to specify whether transfer is to be culled or not.
• The TAB0OPT1.TAB0ID4 to TAB0OPT1.TAB0ID0 bits are used to specify the number of counts by which a
• The TAB0OPT0.TAB0CMS bit is used to specify whether the registers with a transfer function are batch rewritten
interrupt is to be culled.
interrupt is to be culled.
specified interrupt is to be culled.
The interrupt is culled for the duration of the specified number of counts and is generated at the next interrupt
timing.
If it is specified that transfer is to be culled, transfer is executed at the same timing as the interrupt output after
culling. If it is specified that transfer is not to be culled, transfer is executed at the transfer timing after the
TAB0CCR1 register has been written.
or anytime rewritten.
The values of the registers are updated in synchronization with transferring when the TAB0CMS bit is 0. When
the TAB0CMS bit is 1, the values of the registers are immediately updated when a new value is written to the
registers.
Transfer is performed from the TAB0CCRm register to the CCRm buffer register in synchronization with interrupt
culling timing.
Cautions 1. When using the interrupt culling function in the batch rewrite mode (transfer mode),
2. The interrupt is generated at the timing after culling.
execute the function in the intermittent batch rewrite mode (transfer culling mode).
CHAPTER 10 MOTOR CONTROL FUNCTION
User’s Manual U18854EJ2V0UD
533

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