UPD70F3747GB-GAH-AX Renesas Electronics America, UPD70F3747GB-GAH-AX Datasheet - Page 580

• Manufacturer Part Number: UPD70F3747GB-GAH-AX
• Description: MCU 32BIT V850ES/HX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Hx3r

Specifications of UPD70F3747GB-GAH-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3 Registers
578
(1) Watchdog timer mode register 2 (WDTM2)
Cautions 1. For details of the WDCS20 to WDCS24 bits, see Table 12-2 Watchdog Timer 2 Clock
Caution Accessing the WDTM2 register is prohibited in the following statuses. For details, see 3.4.8
The WDTM2 register sets the overflow time and operation clock of watchdog timer 2.
This register can be read or written in 8-bit units. This register can be read any number of times, but it can be
written only once following reset release.
Reset sets this register to 67H.
2. If the WDTM2 register is rewritten twice after reset, an overflow signal is forcibly
3. To intentionally generate an overflow signal, write to the WDTM2 register only twice or
4. To stop the operation of watchdog timer 2, set the RCM.RSTOP bit to 1 (low-speed
WDTM2
Selection.
generated and the counter is reset.
write a value other than ACH to the WDTE register once.
However, when watchdog timer 2 is set to stop operation, an overflow signal is not
generated even if data is written to the WDTM2 register only twice, or a value other than
“ACH” is written to the WDTE register only once.
internal oscillator is stopped), and write 1FH to the WDTM2 register.
(2) Accessing specific on-chip peripheral I/O registers.
•
•
After reset: 67H
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
WDM21
0
0
1
0
CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2
WDM20
WDM21
R/W
0
1
–
Address: FFFFF6D0H
Stops operation
Non-maskable interrupt request mode
(generation of INTWDT2 signal)
Reset mode (generation of WDT2RES signal)
User’s Manual U18854EJ2V0UD
WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
Selection of operation mode of watchdog timer 2