UPD70F3747GB-GAH-AX Renesas Electronics America, UPD70F3747GB-GAH-AX Datasheet - Page 598
UPD70F3747GB-GAH-AX
Manufacturer Part Number
UPD70F3747GB-GAH-AX
Description
MCU 32BIT V850ES/HX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Hx3r
Datasheet
1.UPD70F3747GB-GAH-AX.pdf
(1106 pages)
Specifications of UPD70F3747GB-GAH-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
51
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3747GB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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CHAPTER 13 A/D CONVERTER
(3) Timer trigger mode
In this mode, converting the signal of the analog input pin (ANIn) specified by the ADA0S register is started by
the compare match interrupt request signal (INTTAA2CC0, INTTAA2CC1, or TABTADT0) of the
capture/compare register connected to the timer. The INTTAA2CC0, INTTAA2CC1, or TABTADT0 signal is
selected by the ADA0TMD1 and ADA0TMD0 bits, and conversion is started at the rising edge of the specified
compare match interrupt request signal. When the ADA0CE bit is set to 1, the A/D converter waits for a trigger,
and starts conversion when the compare match interrupt request signal of the timer is input.
When conversion is completed, regardless of whether the continuous select, continuous scan, or one-shot
scan mode is set as the operation mode by the ADA0MD1 and ADA0MD0 bits, the result of the conversion is
stored in the ADA0CRn register. At the same time, the INTAD signal is generated, and the A/D converter waits
for the trigger again.
When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the
A/D converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is
stopped). If the valid trigger is input during the conversion operation, the conversion is aborted and started
again from the beginning.
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during conversion, the
conversion is stopped and the A/D converter waits for the trigger again.
596
User’s Manual U18854EJ2V0UD
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