UPD70F3747GB-GAH-AX Renesas Electronics America, UPD70F3747GB-GAH-AX Datasheet - Page 281

• Manufacturer Part Number: UPD70F3747GB-GAH-AX
• Description: MCU 32BIT V850ES/HX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Hx3r

Specifications of UPD70F3747GB-GAH-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(4) SSCG control register (SSCGCTL)
The SSCGCTL register is an 8-bit register that controls the spread spectrum clock generator (SSCG).
This register can be read or written in 8-bit or 1-bit units.
Cautions 1. Write the SSCGCTL register bits when both PLL and SSCG stop (PLLCTL.PLLON bit =
The relationship between the PLL/SSCG mode and PLLCTL.PLLON/SSCGCTL.SSCGON bit is shown below.
SSCGCTL
PLLCTL.PLLON Bit
2. The SELSSCG bit can be set to 1 only when the SSCGON bit = 1. When the SSCGON
3. If the PLLCTL.PLLON bit is set to 0 or the main clock is stopped while the SSCGON bit
4. When SSCG starts operating, time until SSCG is locked is required.
After reset: 00H
0) or are in the lock status.
bit is set to 0, the SELSSCG bit is automatically set to 0 (PLL output).
= 1, SSCG stops operating.
• If the SSCGON bit is changed from 0 to 1 when the PLLCTL.PLLON bit = 1, make
• If the PLLCTL.PLLON bit is changed from 0 to 1 after the SSCGON bit has been set
• Set a value two times the SSCG lockup time (1 ms or more) to the OSTS register.
0
0
1
1
sure by software that the lockup time of SSCG (1 ms or more) elapses.
to 1, set SSCG lockup time (1 ms or more) to the PLLS register (this is because the
lockup time of SSCG is longer than that of PLL).
SELSSCG
SSCGON
0
1
0
1
0
Table 6-3. Operation Condition of PLL/SSCG Mode
CHAPTER 6 CLOCK GENERATION FUNCTION
PLL output (f
SSCG output (f
SSCG stopped
SSCG operating
R/W
SSCGCTL.SSCGON Bit
0
Selection of clock to be output from multiplication block
User’s Manual U18854EJ2V0UD
Address: FFFFF3F0H
PLL
0
1
0
1
0
PLL
= f
SSCG function operation enable/disable
= f
PLLO
SSCGO
)
0
)
0
PLL Mode
Operates
Stops
0
SELSSCG SSCGON
<1>
SSCG Mode
Operates
Stops
Stops
<0>
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