UPD70F3747GB-GAH-AX Renesas Electronics America, UPD70F3747GB-GAH-AX Datasheet - Page 285

• Manufacturer Part Number: UPD70F3747GB-GAH-AX
• Description: MCU 32BIT V850ES/HX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Hx3r

Specifications of UPD70F3747GB-GAH-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5.3
(1) When PLL is used
(2) When PLL is not used
• Determines a desired frequency by referring Table 6-4 and sets the option byte (OB_7B.PLLO). For details,
• The PLL is stopped (PLLCTL.PLLON bit = 0) after the reset has been released. Operate the main clock
• To stop the PLL, first select the clock-through mode (SELPLL bit = 0), wait for 8 clocks or more, and then
• The PLL stops during transition to IDLE2 or STOP mode regardless of the setting and is restored from
• The clock-through mode (SELPLL bit = 0) is set after the reset has been released. The PLL is stopped
Using PLL
see CHAPTER 27 OPTION BYTE FUNCTION.
(see 6.3 (1) (a) Example of setting high-speed internal oscillation (f
release) and then operate PLL.
To enable PLL operation, first set the PLLON bit to 1, and then set the SELPLL bit to 1 after the
LOCKR.LOCK bit = 0.
stop the PLL (PLLON bit = 0).
IDLE2 or STOP mode to the status before transition. The time required for restoration is as follows.
When shifting to the IDLE1 mode, the PLL does not stop. Stop the PLL if necessary.
(PLLON bit = 0).
(a) When transiting to IDLE2 or STOP mode from the clock through mode
(b) When shifting to the IDLE2 or STOP mode while remaining in the PLL operation mode
(c) When shifting to the IDLE2 or STOP mode while remaining in the SSCG operation mode
• STOP mode: Set the OSTS register so that the oscillation stabilization time is 1600
• IDLE2 mode: Set the OSTS register so that the setup time is 800
• STOP mode: Set the OSTS register so that the oscillation stabilization time is 2 ms or longer.
• IDLE2 mode: Set the OSTS register so that the setup time is 1 ms or longer.
• Set the OSTS register so that the oscillation stabilization time is 54
CHAPTER 6 CLOCK GENERATION FUNCTION
User’s Manual U18854EJ2V0UD
μ
RH
μ
s or longer.
s or longer.
) → main clock (f
μ
s or longer.
X
) after reset
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