UPD70F3747GB-GAH-AX Renesas Electronics America, UPD70F3747GB-GAH-AX Datasheet - Page 75

• Manufacturer Part Number: UPD70F3747GB-GAH-AX
• Description: MCU 32BIT V850ES/HX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Hx3r

Specifications of UPD70F3747GB-GAH-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.3
the FLMD0 and FLMD1 pins.
programmer is connected. In the self-programming mode, however, input a high level to the FLMD0 pin by controlling
the port before rewriting the flash memory after the flash memory has operated in the normal operation mode.
The V850ES/Hx3 has the following operation modes.
• Normal operation mode
• Flash memory programming mode
• Self-programming mode
• On-chip debug mode
The normal operation mode or flash memory programming mode is specified according to the status (input level) of
In the normal mode, input a low level to the FLMD0 pin when reset is released.
In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash programmer if a flash
(1) Normal operation mode
(2) Flash memory programming mode
(3) Self-programming mode
(4) On-chip debug mode
Operation Modes
In this mode, each pin related to the bus interface is set to the port mode after system reset has been released.
Execution branches to the reset entry address of the internal ROM, and then instruction processing is started.
In this mode, the internal flash memory can be programmed by using a flash programmer.
In this mode, the internal flash memory can be erased or written by a user application. For details, see
CHAPTER 26 FLASH MEMORY.
The V850ES/Hx3 is provided with an on-chip debug function that employs the JTAG (Joint Test Action Group)
communication specifications.
For details, see CHAPTER 28 ON-CHIP DEBUG FUNCTION.
Remark
Operation When Reset Is Released
FLMD0
H
H
L
L: Low-level input
H: High-level input
×: Don’t care
FLMD1
H
×
L
CHAPTER 3 CPU FUNCTION
User’s Manual U18854EJ2V0UD
Normal operation mode
Flash memory programming mode
Setting prohibited
Operation Mode After Reset
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