MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 105

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.14.5.2 Entering BDM
4.14.5.3 BDM Commands
MC68HC16Y3/916Y3
USER’S MANUAL
When the CPU16 detects a breakpoint or decodes a BGND instruction when BDM is
enabled, it suspends instruction execution and asserts the FREEZE signal. Once
FREEZE has been asserted, the CPU16 enables the BDM serial communication hard-
ware and awaits a command. Assertion of FREEZE causes opcode tracking signals
IPIPE0 and IPIPE1 to change definition and become serial communication signals
DSO and DSI. FREEZE is asserted at the next instruction boundary after the assertion
of BKPT or execution of the BGND instruction. IPIPE0 and IPIPE1 change function be-
fore an exception signal can be generated. The development system must use
FREEZE assertion as an indication that BDM has been entered. When BDM is exited,
FREEZE is negated before initiation of normal bus cycles. IPIPE0 and IPIPE1 are valid
when normal instruction prefetch begins.
Commands consist of one 16-bit operation word and can include one or more 16-bit
extension words. Each incoming word is read as it is assembled by the serial interface.
The microcode routine corresponding to a command is executed as soon as the
command is complete. Result operands are loaded into the output shift register to be
shifted out as the next command is read. This process is repeated for each command
until the CPU returns to normal operating mode. The BDM command set is summa-
rized in Table 4-7. Refer to the CPU16 Reference Manual (CPU16RM/AD) for a BDM
command glossary.
Read Program Memory
Write Program Memory
Read MAC Registers
Execute from Current
Write MAC Registers
Read Data Memory
Write Data Memory
Read PC and SP
Write PC and SP
Read Registers
Write Registers
Null Operation
Command
from Mask
from Mask
PK : PC
Table 4-7 Command Summary
Mnemonic
WDMEM
WREGM
WRMAC
WPMEM
RREGM
RDMEM
RPMEM
RDMAC
WPCSP
RPCSP
NOP
GO
Read contents of registers specified by command
word register mask
Write to registers specified by command word
register mask
Read contents of entire multiply and accumulate
register set
Write to entire multiply and accumulate register set
Read contents of program counter and stack pointer
Write to program counter and stack pointer
Read byte from specified 20-bit address in data
space
Write byte to specified 20-bit address in data space
Read word from specified 20-bit address in program
space
Write word to specified 20-bit address in program
space
Instruction pipeline flushed and refilled; instructions
executed from current PC – $0006
Null command performs no operation
Description
MOTOROLA
4-43