MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 313

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.3.4 Programmable Channel Service Priority
14.3.5 Coherency
14.3.6 Emulation Support
14.3.7 TPU2 Interrupts
MC68HC16Y3/916Y3
USER’S MANUAL
The TPU2 provides a programmable service priority level to each channel. Three pri-
ority levels are available. When more than one channel of a given priority requests ser-
vice at the same time, arbitration is accomplished according to channel number. To
prevent a single high-priority channel from permanently blocking other functions, other
service requests of the same priority are performed in channel order after the lowest-
numbered, highest-priority channel is serviced.
For data to be coherent, all available portions of the data must be identical in age, or
must be logically related. As an example, consider a 32-bit counter value that is read
and written as two 16-bit words. The 32-bit value is read-coherent only if both 16-bit
portions are updated at the same time, and write-coherent only if both portions take
effect at the same time. Parameter RAM hardware supports coherent access of two
adjacent 16-bit parameters. The host CPU must use a long-word operation to guaran-
tee coherency.
Although factory-programmed time functions can perform a wide variety of control
tasks, they may not be ideal for all applications. The TPU2 provides emulation capa-
bility that allows the user to develop new time functions. Emulation mode is entered by
setting the EMU bit in TPUMCR. In emulation mode, an auxiliary bus connection is
made between the TPUFLASH and the TPU2, and access to TPUFLASH via the
intermodule bus is disabled. A 9-bit address bus, a 32-bit data bus, and control lines
transfer information between the modules. To ensure exact emulation, TPUFLASH
module access timing remains consistent with access timing of the TPU microcode
ROM control store.
To support changing TPU application requirements, Motorola has established a TPU
function library. The function library is a collection of TPU functions written for easy
assembly in combination with each other or with custom functions. Refer to Motorola
Programming Note TPUPN00/D, Using the TPU Function Library and TPU Emulation
Mode for information about developing custom functions and accessing the TPU func-
tion library. Refer to the TPU Reference Manual (TPURM/AD) and the Motorola TPU
Literature Package (TPULITPAK/D) for more information about specific functions.
Each of the TPU2 channels can generate an interrupt service request. Interrupts for
each channel must be enabled by writing to the appropriate control bit in the channel
interrupt enable register (CIER). The channel interrupt status register (CISR) contains
one interrupt status flag per channel. Time functions set the flags. Setting a flag bit
causes the TPU2 to make an interrupt service request if the corresponding channel
interrupt enable bit is set and the interrupt request level is non-zero.
TIME PROCESSOR UNIT 2
MOTOROLA
14-5