MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 281

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.4.1.2 SCI Status Register
12.4.1.3 SCI Data Register
12.4.2 SCI Pins
MC68HC16Y3/916Y3
USER’S MANUAL
SCCR1 contains a number of SCI configuration parameters, including transmitter and
receiver enable bits, interrupt enable bits, and operating mode enable bits. The
CPU16 can read and write this register at any time. The SCI can modify the RWU bit
under certain circumstances.
Changing the value of SCI control bits during a transfer may disrupt operation. Before
changing register values, allow the SCI to complete the current transfer, then disable
the receiver and transmitter.
The SCSR contains flags that show SCI operating conditions. These flags are cleared
either by SCI hardware or by a read/write sequence. To clear SCI transmitter flags,
read the SCSR and then write to the SCDR. To clear SCI receiver flags, read the
SCSR and then read the SCDR. A long-word read can consecutively access both the
SCSR and the SCDR. This action clears receiver status flag bits that were set at the
time of the read, but does not clear TDRE or TC flags.
If an internal SCI signal for setting a status bit comes after the CPU has read the
asserted status bits, but before the CPU has written or read the SCDR, the newly set
status bit is not cleared. The SCSR must be read again with the bit set, and the SCDR
must be written to or read before the status bit is cleared.
Reading either byte of the SCSR causes all 16 bits to be accessed, and any status bit
already set in either byte will be cleared on a subsequent read or write of the SCDR.
The SCDR contains two data registers at the same address. The RDR is a read-only
register that contains data received by the SCI serial interface. The data comes into
the receive serial shifter and is transferred to the RDR. The TDR is a write-only register
that contains data to be transmitted. The data is first written to the TDR, then trans-
ferred to the transmit serial shifter, where additional format bits are added before trans-
mission.
Four pins are associated with the SCI: TXDA, TXDB, RXDA, and RXDB. The state of
the TE or RE bit in SCI control register 1 of each SCI submodule (SCCR1A, SCCR1B)
determines whether the associated pin is configured for SCI operation or general-pur-
pose I/O. The MDDR assigns each pin as either input or output. The WOMC bit in
SCCR1A or SCCR1B determines whether the associated RXD and TXD pins, when
configured as outputs, function as open-drain output pins or normal CMOS outputs.
The MDDR and WOMC assignments are valid regardless of whether the pins are con-
figured for SPI use or general-purpose I/O.
SCI pins are listed in Table 12-5.
MULTICHANNEL COMMUNICATION INTERFACE
MOTOROLA
12-17