MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 147

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.6.6.1 Show Cycles
MC68HC16Y3/916Y3
USER’S MANUAL
This additional BG assertion allows external arbitration circuitry to select the next bus
master before the current master has released the bus.
Refer to Figure 5-16, which shows bus arbitration for a single device. The flow chart
shows BR negated at the same time BGACK is asserted.
The MCU normally performs internal data transfers without affecting the external bus,
but it is possible to show these transfers during debugging. AS is not asserted exter-
nally during show cycles.
Show cycles are controlled by the SHEN[1:0] in SCIMCR. This field set to %00 by re-
set. When show cycles are disabled, the address bus, function codes, size, and read/
write signals reflect internal bus activity, but AS and DS are not asserted externally and
external data bus pins are in high-impedance state during internal accesses. Refer to
5.2.4 Show Internal Cycles and the SCIM Reference Manual (SCIMRM/AD) for more
information.
When show cycles are enabled, DS is asserted externally during internal cycles, and
internal data is driven out on the external data bus. Because internal cycles normally
continue to run when the external bus is granted, one SHEN[1:0] encoding halts inter-
nal bus activity while there is an external master.
RE-ARBITRATE OR RESUME PROCESSOR
1) ASSERT BUS GRANT (BG)
1) NEGATE BG (AND WAIT FOR
Figure 5-16 Bus Arbitration Flowchart for Single Request
BGACK TO BE NEGATED)
GRANT BUS ARBITRATION
TERMINATE ARBITRATION
OPERATION
MCU
1) PERFORM DATA TRANSFERS (READ AND
1) NEGATE BGACK
1) ASSERT BUS REQUEST (BR)
1) EXTERNAL ARBITRATION DETERMINES
2) NEXT BUS MASTER WAITS FOR BGACK
3) NEXT BUS MASTER ASSERTS BGACK
4) BUS MASTER NEGATES BR
WRITE CYCLES) ACCORDING TO THE SAME
RULES THE PROCESSOR USES
NEXT BUS MASTER
TO BE NEGATED
TO BECOME NEW MASTER
ACKNOWLEDGE BUS MASTERSHIP
RELEASE BUS MASTERSHIP
OPERATE AS BUS MASTER
REQUESTING DEVICE
REQUEST THE BUS
MOTOROLA
BUS ARB FLOW
5-39