MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 395

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

D.2.20 Port F Edge-Detect Interrupt Vector
PFIVR — Port F Edge-Detect Interrupt Vector Register
D.2.21 Port F Edge-Detect Interrupt Level
PFLVR — Port F Edge-Detect Interrupt Level Register
D.2.22 Port C Data Register
PORTC — Port C Data Register
MC68HC16Y3/916Y3
USER’S MANUAL
15
15
15
RESET:
RESET:
RESET:
When the corresponding pin is configured for edge detection, a PORTFE bit is set if
an edge is detected. PORTFE bits remain set, regardless of the subsequent state of
the corresponding pin, until cleared. To clear a bit, first read PORTFE, then write the
bit to zero. When a pin is configured for general-purpose I/O or for use as an interrupt
request input, PORTFE bits do not change state. Bits [15:8] are unimplemented and
will always read zero.
This register determines which vector in the exception vector table is used for inter-
rupts generated by the port F edge-detect logic. Program PFIVR[7:0] to the value
pointing to the appropriate interrupt vector. Bits [15:8] are unimplemented and will al-
ways read zero.
This register determines the priority level of the port F edge-detect interrupt. The reset
value is $00, indicating that the interrupt is disabled. When several sources of inter-
rupts from the SCIM are arbitrating for the same level, the port F edge-detect interrupt
has the lowest arbitration priority. Bits [15:8] are unimplemented and will always read
zero.
PORTC latches data for chip-select pins configured as discrete outputs.
14
14
13
13
12
12
NOT USED
NOT USED
NOT USED
11
11
10
10
REGISTER SUMMARY
9
9
8
8
8
7
0
7
0
0
7
0
0
PC6
6
0
6
0
0
6
1
PC5
5
0
5
0
0
5
1
PC4
4
0
4
0
0
4
1
PFIVR[7:0]
PC3
3
0
3
0
0
3
1
PC2
2
0
2
0
2
1
$YFFA2A
$YFFA2C
PFLV[2:0]
$YFFA41
MOTOROLA
PC1
1
0
1
0
1
1
D-17
PC0
0
0
0
0
0
1